One direction-shift register aliasing table circuit suitable for use in microprocessors
OwnerOguz Ergin, Ilker Polatinventors
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Abstract
Disclosed are hardware configurations of the Register Aliasing Table (RAT) which are suitable for use in structures such as modern microprocessor, microcontroller, CPU etc. that use pipe line technique, perform multi-command operations, prevents Write After Read (WAR), Write After Write (WAW), Read After Write (RAW) dependencies. The Register Aliasing Table provides a circuit which consumes less energy, uses less space and has low latency compared to the applications in the state of the art.
Claims3
A register aliasing table for use in microprocessors, microcontrollers, or CPUs that use a pipeline technique in order to perform multi-command operations, to prevent write after read, to prevent write after write, or to prevent read after write, the risks register aliasing table comprising:
- a predetermined number of adjacently ordered printer drivers which are adapted to be activated during a writing process;
- a pre-charge block ordered side-by-side and having a same number of buses as a number of buses of said predetermined number of adjacently ordered printer drivers, the buses of said pre-charge block being connected to the buses of said predetermined number of adjacently ordered printer drivers and adapted to ensure that the buses of said predetermined number of adjacently ordered printer drivers wait in a stable manner when reading or writing is not performed;
- a static random-access memory (SRAM) cell block having a plurality of cell groups that are interconnectedly arranged with each other so as to have a number of columns connected to said pre-charge block with an equal number of buses and a number of rows;
- a second decoder that determines a row in which information in the cell group of the plurality of cell groups is to be copied and adapted to execute commands that informs which row is referred to for information to perform the process, said second decoder having an outlet that is connected to each row of the SRAM cell block;
- a plurality of sense amplifiers that are connected via buses to said SRAM cell block in proportion to the number of columns, said plurality of sense amplifiers being arranged adjacent to each other in proportion to a number of adapted columns so as to bring a low output to a higher output that can be read;
- a plurality of multiplexers connected to said plurality of sense amplifiers via buses in proportion to the number of columns, said plurality of multiplexers being arranged next to each other in proportion to the number of adapted columns so as to select from which output of the cell group of said plurality of cell groups is required for reading;
- and
- a first decoder which determines which cell group in the SRAM cell block the reading and writing will be performed, said first decoder determining which input is to be selected by a plurality of multiplexers and determines which write driver and pre-charge block and sense amplifier arranged adjacent to each other will operate.
Dependencies are inferred from the claim text.