Interrupt request signal conversion system and method, and computing device

A computing device comprising:

• a processor including an interface module and an interrupt controller;
• and
• an interrupt request signal conversion system including:
• an interrupt request signal converter configured to generate one or more converted interrupt request signals based on one or more signals received from a plurality of peripheral devices, each of the one or more converted interrupt request signals including a plurality of interrupt identification bits each used to identify, based on a first level and a second level different from the first level, whether a signal received from a corresponding one of the one or more peripheral devices within a predetermined time range includes a peripheral interrupt request signal;
• a plurality of interrupt request signal input terminals configured to be coupled to the plurality of peripheral devices, respectively;
• and
• a signal output terminal configured to send the one or more converted interrupt request signals to the interface module of the processor during operation;
• wherein:
• the interface module includes an interface controller configured to report an interrupt request of the peripheral device requesting interrupt to the interrupt controller based on the one or more converted interrupt request signals;
• the interrupt request signal converter is further configured to receive one or more interrupt reference level signals corresponding to the one or more converted interrupt request signals from the interface module;
• wherein each of the one or more interrupt reference level signals includes including a start frame, an end frame, and a blank frame located between the start frame and the end frame;
• in response to the signals received from the plurality of peripheral devices including N peripheral interrupt request signals, N being a positive integer, the interrupt request signal converter is further configured to:
• receive the N peripheral interrupt request signals from the plurality of interrupt request signal input terminals within one or more clock cycles occupied by a same one of the one or more interrupt reference level signals;
• generate, based on the N peripheral interrupt request signals, a plurality of intermediate signals within one or more clock cycles occupied by the blank frame of a first interrupt reference level signal among the one or more interrupt reference level signals that is first received after the N peripheral interrupt request signals are received;
• and
• perform a logical AND operation on the plurality of intermediate signals to generate one converted interrupt request signal of the one or more converted interrupt request signals that corresponds to the first interrupt reference level signal;
• each of the intermediate signals includes an interrupt identification bit corresponding to the interrupt request signal input terminal coupled to a sub-converter that outputs each of the intermediate signals;
• the plurality of interrupt request signal input terminals are configured to receive the N peripheral interrupt request signals;
• and
• the peripheral interrupt request signal corresponding to the first interrupt reference level signal includes the N interrupt request identifiers.

An interrupt request signal conversion method comprising:

• generating, by an interrupt request signal converter, one or more converted interrupt request signals based on one or more signals received from a plurality of peripheral devices, a plurality of interrupt request signal input terminals being configured to be coupled to the plurality of peripheral devices, respectively;
• and
• sending, by a signal output terminal, the one or more converted interrupt request signals to an interface module of a processor during operation;
• wherein:
• each of the converted interrupt request signals includes a plurality of interrupt identification bits, each of the one or more converted interrupt request signals including a plurality of interrupt identification bits each used to identify, based on a first level and a second level different from the first level, whether a signal received from a corresponding one of the one or more peripheral devices within a predetermined time range includes a peripheral interrupt request signal;
• the interrupt request signal converter is further configured to receive one or more interrupt reference level signals corresponding to the one or more converted interrupt request signals from the interface module;
• wherein each of the one or more interrupt reference level signals includes including a start frame, an end frame, and a blank frame located between the start frame and the end frame;
• in response to the signals received from the plurality of peripheral devices including N peripheral interrupt request signals, N being a positive integer, the interrupt request signal converter is further configured to:
• receive the N peripheral interrupt request signals from the plurality of interrupt request signal input terminals within one or more clock cycles occupied by a same one of the one or more interrupt reference level signals;
• generate, based on the N peripheral interrupt request signals, a plurality of intermediate signals within one or more clock cycles occupied by the blank frame of a first interrupt reference level signal among the one or more interrupt reference level signals that is first received after the N peripheral interrupt request signals are received;
• and
• perform a logical AND operation on the plurality of intermediate signals to generate one converted interrupt request signal of the one or more converted interrupt request signals that corresponds to the first interrupt reference level signal;
• each of the intermediate signals includes an interrupt identification bit corresponding to the interrupt request signal input terminal coupled to a sub-converter that outputs each of the intermediate signals;
• the plurality of interrupt request signal input terminals are configured to receive the N peripheral interrupt request signals;
• and
• the peripheral interrupt request signal corresponding to the first interrupt reference level signal includes the N interrupt request identifiers.