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US 11,810,964 B2Granted
Semiconductor devices including gate spacer
AssigneeSamsung Electronics Co., Ltd.
InventorsBongseok Suh, Daewon Kim, Beomjin Park, Sukhyung Park, Sungil Park, Jaehoon Shin, Bongseob Yang, Junggun You, Jaeyun Lee
Life of this patent
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Abstract
A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.
Claims17
A semiconductor device, comprising:
- a first active region defined on a substrate;
- a first gate electrode across the first active region;
- a first drain region in the first active region at a position adjacent to the first gate electrode;
- an undercut region between the first active region and a metal portion of the first gate electrode;
- a first gate spacer on a side surface of the first gate electrode and protruding into the undercut region, wherein the first gate spacer includes
- an upper portion on the side surface of the first gate electrode, and
- a lower portion extending from the upper portion into the undercut region,
- wherein the first active region comprises a plurality of channel regions, each of the plurality of channel regions being in contact with the first drain region, and
- wherein the first gate electrode surrounds a top surface, a side surface, and a bottom surface of at least one of the plurality of channel regions;
- and
- a first gate dielectric layer between the first gate electrode and the plurality of channel regions and extending between the first gate electrode and the first gate spacer, the first gate dielectric layer being in contact with a side surface and a top surface of the lower portion,
- wherein the undercut region is between the metal portion of the first gate electrode and an uppermost channel region of the plurality of channel regions.
9 more elements
A semiconductor device, comprising:
- a first active region defined in a first region on a substrate;
- a first gate electrode across the first active region;
- a first gate dielectric layer between the first active region and the first gate electrode;
- a first drain region in the first active region at a position adjacent to the first gate electrode;
- an undercut region between the first active region and a metal portion of the first gate electrode;
- a first gate spacer on a side surface of the first gate electrode and protruding into the undercut region;
- a second active region defined in a second region on the substrate;
- a second gate electrode across the second active region and having a larger horizontal width than the first gate electrode;
- a second drain region in the second active region at a position adjacent to the second gate electrode;
- a lower gate dielectric layer between the second active region and the second gate electrode, wherein the lower gate dielectric layer has a larger horizontal width than the second gate electrode;
- and
- a second gate spacer on a side surface of the second gate electrode.
9 more elements
A semiconductor device, comprising:
- a first active region defined in a first region on a substrate;
- a first gate electrode across the first active region;
- a first gate dielectric layer between the first active region and the first gate electrode;
- a pair of first drain regions in the first active region at positions adjacent to opposite sides of the first gate electrodes and spaced apart from each other;
- an undercut region between the first active region and the first gate electrode;
- a first gate spacer on a side surface of the first gate electrode and extending into the undercut region;
- a second active region defined in a second region on the substrate;
- a second gate electrode across the second active region and having a larger horizontal width than the first gate electrode;
- a second gate dielectric layer between the second active region and the second gate electrode;
- a pair of second drain regions in the second active region at positions adjacent to opposite sides of the second gate electrodes and spaced apart from each other;
- a lower gate dielectric layer between the second active region and the second gate dielectric layer and having a larger horizontal width than the second gate electrode;
- and
- a second gate spacer on a side surface of the second gate electrode,
- wherein the first active region includes a plurality of channel regions, each of the plurality of channel regions being in contact with the pair of first drain regions,
- wherein the first gate electrode surrounds a top surface, a side surface, and a bottom surface of at least one of the plurality of channel regions, and
- wherein the second gate electrode is on a top surface and a side surface of the second active region, a lower end of the second gate electrode being at a lower level than an upper end of the second active region.
13 more elements
Dependencies are inferred from the claim text.