US 11,810,747 B2 · Wafer scale enhanced gain electron bombarded CMOS imager

Abstract

An apparatus, system and method is provided for producing stacked wafers containing an array of image intensifiers that can be evacuated on a wafer scale. The wafer scale fabrication techniques, including bonding, evacuation, and compression sealing concurrently forms a plurality of EBCMOS imager anodes with design elements that enable high voltage operation with optional enhancement of additional gain via TMSE amplification. The TMSE amplification is preferably one or more multiplication semiconductor wafers of an array of EBD die placed between a photocathode within a photocathode wafer and an imager anode that is preferably an EBCMOS imager anode bonded to or integrated within an interconnect die within an interconnect wafer.

Claims15

Dependent claims

An image intensifier apparatus, comprising:

a photocathode wafer comprising a plurality of photocathode regions;
an interconnect wafer comprising a plurality of electrically separate sets of conductive traces formed in or upon the interconnect wafer;
a plurality of imager anodes integrated among or bonded to corresponding electrically separate sets of conductive traces;
an insulative spacer wafer with openings therein aligned over the imager anodes and between the interconnect wafer and the photocathode wafer;
and
gaps within each space of a plurality of spaces formed between each imager anode of the plurality of imager anodes and each of the respective plurality of photocathodes through which the plurality of spaces are simultaneously evacuated to concurrently form a plurality of image intensifiers thereafter diced to form the image intensifier apparatus.

3 more elements

Dependencies are inferred from the claim text.

Wafer scale enhanced gain electron bombarded CMOS imager

Life of this patent

Wafer scale enhanced gain electron bombarded CMOS imager

Life of this patent

Abstract

Claims15