US 11,810,636 B2Granted

Latch array with mask-write functionality

AssigneeQUALCOMM Incorporated

InventorsRui Li, De Lu, Venkat Narayanan

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Abstract

An aspect of the disclosure relates to a latch array, including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs coupled to a set of bitlines, respectively; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively; and an array of slave latches, wherein the slave latches in columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively.

Claims27

Dependent claims

A latch array, comprising:

a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data, and a first set of data outputs coupled to a set of bitlines, respectively;
a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively;
an array of slave latches arranged into columns and rows, wherein the slave latches in the columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively, wherein each slave latch of the array comprises:
a clock gating circuit including one of the second set of write-bit inputs coupled to one of the set of write-bit lines, one of the fourth set of clock inputs coupled to one of the set of wordlines, and complementary clock outputs,
a data gating circuit including one of the second set of data inputs coupled to one of the set of bitlines, a first set of complementary clock inputs coupled to the complementary clock outputs of the clock gating circuit, respectively, and a first data output, and
a data latching circuit including a second set of complementary clock inputs coupled to the complementary clock outputs of the clock gating circuit, respectively, a data input coupled to the first data output of the data gating circuit, and a second data output and
a set of clock gating circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of wordlines, wherein the slave latches in the rows of the array include a fourth set of clock inputs coupled to the set of wordlines, respectively.

4 more elements

A latch array, comprising:

a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data, and a first set of data outputs coupled to a set of bitlines, respectively;
a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively;
an array of slave latches arranged into columns and rows, wherein the slave latches in the columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively;
and
a set of clock gating circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of wordlines, wherein the slave latches in the rows of the array include a fourth set of clock inputs coupled to the set of wordlines, respectively,
wherein each slave latch of the array comprises:
a clock gating circuit, comprising:
a NOR gate including a first input serving as one of the second set of write-bit inputs coupled to one of the set of write-bit lines, a second input serving as one of the fourth set of clock inputs coupled to one of the set of wordlines, and an output;
and
a first inverter including an input coupled to the output of the NOR gate, and an output;
a data gating circuit, comprising:
a first field effect transistor (FET) including a first gate serving as one of the second set of data inputs coupled to one of the set of bitlines;
a second FET including a second gate coupled to the output of the first inverter;
a third FET including a third gate coupled to the output of the NOR gate;
and
a fourth FET including a fourth gate coupled to the first gate of the first FET, wherein the first, second, third, and fourth FETs are coupled in series between first and second voltage rails;
and
a data latching circuit, comprising:
a fifth FET including a fifth gate coupled to an output of the data latching circuit;
a sixth FET including a sixth gate coupled to the output of the NOR gate;
a seventh FET including a seventh gate coupled to the output of the first inverter;
an eighth FET including an eighth gate coupled to the fifth gate of the fifth FET, wherein the fifth, sixth, seventh, and eighth FETs are coupled in series between the first and second voltage rails;
and
a second inverter including an input coupled to a node between the sixth and seventh FETs, and an output coupled to the output of the data latching circuit.

21 more elements

A latch array, comprising:

a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data, and a first set of data outputs coupled to a set of bitlines, respectively;
a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively;
an array of slave latches arranged into columns and rows, wherein the slave latches in the columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively;
and
a set of clock gating circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of wordlines, wherein the slave latches in the rows of the array include a fourth set of clock inputs coupled to the set of wordlines, respectively,
wherein each slave latch of the array comprises:
a signal buffer circuit, comprising:
a first inverter including an input serving as one of the fourth set of clock inputs coupled to one of the wordlines, and an output;
a second inverter including an input coupled to the output of the first inverter, and an output;
a third inverter including an input serving as one of the second set of write-bit inputs coupled to one of the set of write-bit lines, and an output;
and
a fourth inverter including an input coupled to the output of the third inverter, and an output;
a data gating circuit, comprising:
a first field effect transistor (FET) including a first gate coupled to one of the second set of data inputs coupled to one of the set of bitlines;
a second FET including a second gate coupled to the output of the second inverter;
a third FET including a third gate coupled to the output of the fourth inverter;
a fourth FET including a fourth gate coupled to the output of the third inverter;
a fifth FET including a fifth gate coupled to the output of the first inverter;
a sixth FET including a sixth gate coupled to the first gate of the first FET, wherein the first, second, third, fourth, fifth, and sixth FETs are coupled in series between first and second voltage rails;
and
a data latching circuit, comprising:
a seventh FET including a seventh gate coupled to an output of the data latching circuit;
a first pair of parallel FETs including gates coupled to the outputs of the first and third inverters, respectively;
a second pair of parallel FETs including gates coupled to the outputs of the second and fourth inverters, respectively;
an eighth FET including an eighth gate coupled to the seventh gate of the seventh FET, wherein the seventh FET, the first pair of parallel FETs, the second pair of parallel FETs, and the eighth FET are coupled in series between the first and second voltage rails;
and
a fifth inverter including an input coupled to a node between the first and second pairs of parallel FETs, and an output coupled to the output of the data latching circuit.

24 more elements

A latch array, comprising:

a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data, and a first set of data outputs coupled to a set of bitlines, respectively;
a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively;
an array of slave latches arranged into columns and rows, wherein the slave latches in the columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively;
and
a set of clock gating circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of wordlines, wherein the slave latches in the rows of the array include a fourth set of clock inputs coupled to the set of wordlines, respectively,
wherein each slave latch of the array comprises:
a signal buffer circuit, comprising:
a first inverter including an input serving as one of the fourth set of clock inputs coupled to one of the wordlines, and an output;
a second inverter including an input coupled to the output of the first inverter, and an output;
a third inverter including an input serving as one of the second set of write-bit inputs coupled to one of the set of write-bit lines, and an output;
and
a fourth inverter including an input coupled to the output of the third inverter, and an output;
a multiplexer, comprising:
a first transmission gate including a first terminal coupled to one of the second set of data inputs coupled to one of the set of bitlines, a first set of complementary gates coupled to the outputs of the third and fourth inverters, respectively, and a second terminal;
and
a second transmission gate including a third terminal, a second set of complementary gates coupled to the outputs of the third and fourth inverters, respectively, and a fourth terminal coupled to the second terminal to form an output;
and
a data gating circuit, comprising:
a first field effect transistor (FET) including a first gate coupled to the output of the multiplexer;
a second FET including a second gate coupled to the output of the second inverter;
a third FET including a third gate coupled to the output of the first inverter;
and
a fourth FET including a fourth gate coupled to the first gate of the first FET, wherein the first, second, third, and fourth FETs are coupled in series between first and second voltage rails;
and
a data latching circuit, comprising:
a fifth FET including a fifth gate coupled to an output of the data latching circuit;
a sixth FET including a sixth gate coupled to the output of the first inverter;
a seventh FET including a seventh gate coupled to the output of the second inverter;
an eighth FET including an eighth gate coupled to the fifth gate of the fifth FET, wherein the fifth, sixth, seventh, and eighth FETs are coupled in series between the first and second voltage rails;
and
a fifth inverter including an input coupled to a node between the sixth and seventh FETs, and an output coupled to the output of the data latching circuit, wherein the output of the data latching circuit is coupled to the third terminal of the second transmission gate.

28 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/574,431Filed 12 Jan 2022
Published: US 2023/0223054 A113 Jul 2023
Granted: 7 Nov 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 7/1009
Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor: data masking during input/output
G11C 19/28
Digital stores in which the information is moved stepwise, e.g. shift registers: using semiconductor elements
G11C 7/1087
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input latches
G11C 19/287
Using semiconductor elements: organisation of a multiplicity of shift registers