Implementing large multipliers in tensor arrays
AssigneeIntel Corporation
InventorsMartin Langhammer, Simon Peter Finn
Life of this patent
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Abstract
The present disclosure describes an integrated circuit device that includes a digital signal processing (DSP) block. The DSP block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Also, the first plurality of inputs, the second plurality of inputs, or both are derived from higher precision values. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.
Claims20
An integrated circuit device comprising:
- a digital signal processing (DSP) block comprising:
- a plurality of columns of weight registers;
- a plurality of inputs configurable to receive a first plurality of values and a second plurality of values, wherein the first plurality of values is stored in the plurality of columns of weight registers after being received, wherein the first plurality of values, the second plurality of values, or both are derived from higher precision values;
- and
- a plurality of multipliers configurable to:
- simultaneously multiply each value of the first plurality of values by each value of the second plurality of values. and
- emulate one or more multipliers that perform multiplication operations involving higher precision data types relative to a data type of the first plurality of values or the second plurality of values.
An integrated circuit device comprising:
- a plurality of digital signal processing (DSP) blocks, wherein each of the plurality of DSP blocks comprises:
- a plurality of columns of registers;
- a plurality of inputs configurable to receive a first plurality of values and a second plurality of values, wherein the first plurality of values is stored in the plurality of columns of registers after being received, wherein the first plurality of inputs values, the second plurality of values, or both are derived from higher precision values;
- and
- a plurality of multipliers configurable to:
- simultaneously multiply each value of the first plurality of values by each value of the second plurality of values;
- and
- emulate one or more multipliers that perform multiplication operations involving higher precision data types relative to a data type of the first plurality of values or the second plurality of values.
A system comprising:
- an integrated circuit device;
- and
- a programmable logic device communicatively coupled to the integrated circuit device, wherein the programmable logic device comprises a plurality of digital signal processing (DSP) blocks, wherein each of the plurality of DSP blocks comprises:
- a plurality of columns of weight registers;
- a plurality of inputs configurable to receive a first plurality of values and a second plurality of values, wherein the first plurality of values is stored in the plurality of columns of weight registers after being received, wherein the first plurality of values, the second plurality of values, or both are derived from higher precision values;
- and
- a plurality of multipliers configurable to:
- simultaneously multiply each value of the first plurality of values by each value of the second plurality of values;
- and
- emulate one or more multipliers that perform multiplication operations involving higher precision data types relative to a data type of the first plurality of values or the second plurality of values.
Dependencies are inferred from the claim text.