Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures

An apparatus, comprising:

• a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals,
• wherein the driver circuit comprising a plurality of drivers configured to drive the plurality of respective multilevel signals onto a plurality of respective signal lines, and
• wherein each driver of the plurality of drivers is configured to drive more than two voltages, and
• wherein a number of the plurality of bitstreams is greater than a number of the plurality of multilevel signals,
• wherein the plurality of drivers comprise a plurality of signal line drivers having a same impedance,
• wherein the driver circuit comprises a first driver section controlled by a first control signal associated with the first plurality of bitstreams and a second driver section controlled by a second control signal associated with the second plurality of bitstreams,
• wherein the first driver section comprises a first number of signal line drivers of the plurality of signal line drivers,
• wherein the second driver section comprises a second number of the signal line drivers of the plurality of signal line drivers, and
• wherein the first number and the second number are different from each other.

A method comprising:

• receiving, at a receiver comprising a plurality of comparators, a plurality of multilevel signals including a first multilevel signal and a second multilevel signal;
• providing, by the plurality of comparators, a plurality of output signals based on a first reference voltage and a second reference voltage responsive to any multilevel signal of the plurality of multilevel signals, including:
• providing a first output signal and a second output signal based on the first reference voltage and the second reference voltage respectively, responsive to the first multilevel signal;
• and
• providing a third output signal and a fourth output signal based on the first reference voltage and the second reference voltage respectively, responsive to the second multilevel signal;
• providing, by the receiver, a plurality of bitstreams responsive to the first, second, third and fourth output signals, wherein the plurality of bitstreams are greater in number than the plurality of multilevel signals;
• receiving, by a decoder, the first and second output signals from a first circuit provided responsive to the first multilevel signal;
• receiving, by the decoder, the third and fourth output signals from a second circuit provided responsive to the second multilevel signal;
• and
• providing, by the decoder, a first bitstream, a second bitstream and a third bitstream responsive to the first, second, third and fourth output signals.

A method comprising:

• receiving, at a receiver comprising a plurality of comparators, a plurality of multilevel signals including a first multilevel signal and a second multilevel signal;
• providing, by the plurality of comparators, a plurality of output signals based on a first reference voltage and a second reference voltage responsive to any multilevel signal of the plurality of multilevel signals, including:
• providing a first output signal and a second output signal based on the first reference voltage and the second reference voltage respectively, responsive to the first multilevel signal;
• and
• providing a third output signal and a fourth output signal based on the first reference voltage and the second reference voltage respectively, responsive to the second multilevel signal;
• providing, by the receiver, a plurality of bitstreams responsive to the first, second, third and fourth output signals, wherein the plurality of bitstreams are greater in number than the plurality of multilevel signals;
• receiving the first and second output signals from a first circuit;
• receiving the third and fourth output signals from a second circuit;
• providing a first bitstream, a second bitstream and a third bitstream responsive to the first, second, third and fourth output signals;
• receiving the first, second and third output signals;
• providing a first intermediate signal responsive to the first, second and third output signals;
• receiving the first, second and fourth output signals;
• providing a second intermediate signal responsive to the first, second and fourth output signals;
• receiving the first and second intermediate signals;
• providing the first bitstream responsive to the first and second intermediate signals;
• receiving the first, second, third and fourth output signals;
• providing a third intermediate signal responsive to the first, second, third and fourth output signals;
• receiving the first, second, third and fourth output signals;
• providing a fourth intermediate signal responsive to the first, second, third and fourth output signals;
• receiving the first, second and third output signals;
• providing a fifth intermediate signal responsive to the first, second and third output signals;
• receiving the third, fourth and fifth intermediate signals;
• and
• providing the second bitstream responsive to the third, fourth and fifth intermediate signals.

A method, comprising:

• converting a plurality of bitstreams into a plurality of multilevel signals by a driver circuit;
• driving the plurality of respective multilevel signals onto a plurality of respective signal lines by the driver circuit;
• controlling a first driver section in the driver circuit by a first control signal associated with the first plurality of bitstreams;
• and
• controlling a second driver section in the driver circuit by a second control signal associated with the second plurality of bitstreams,
• wherein the plurality of multilevel signals have more than two signal levels,
• wherein a number of the plurality of bitstreams is greater than a number of the multilevel signals,
• wherein the first and second control signals are generated based on the plurality of bitstreams, further comprising:
• driving an output signal onto the plurality of respective signal lines by a first driver responsive to a first plurality of bitstreams of the plurality of bitstreams;
• and
• driving the output signal onto the plurality of respective signal lines by a second driver responsive to a second plurality of bitstreams of the plurality of bitstreams.