System, device and method for indirect addressing
AssigneeSamsung Electronics Co., Ltd.
InventorsJeongho Lee, Ipoom Jeong, Younggeon Yoo, Younho Jeon
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Abstract
A method performed by a device connected to a host processor via a bus includes: providing a first read request including a first address to a memory; receiving a second address stored in a first region of the memory corresponding to the first address, from the memory; providing a second read request including the second address to the memory; and receiving first data stored in a second region of the memory corresponding to the second address, from the memory, wherein the first read request further includes information indicating that the first address is an indirect address of the first data.
Claims18
A memory controller configured to control a memory accessed by a device connected to a host processor via a bus, wherein the device comprises an accelerator circuit, the memory controller comprising:
- a first interface circuit configured to communicate with the device;
- a second interface circuit configured to communicate with the memory;
- a write circuit configured to store first data in the memory based on indirect addressing;
- and
- a read circuit configured to:
- identify that a first address included in a first read request received via the first interface circuit from the accelerator circuit is an indirect address of the first data, based on first information included in the first read request,
- read a second address from a first region of the memory via the second interface circuit, the first region corresponding to the first address,
- in response to the first read request, provide the second address to the accelerator circuit of the device via the first interface circuit, and
- prefetch the first data from a second region of the memory via the second interface circuit, the second region corresponding to the second address,
- wherein the read circuit is further configured to perform the prefetch by providing a second read command to the memory, together with the second address, without an additional read request issued with respect to the first read request by the accelerator circuit.
A system comprising:
- a host processor comprising at least one core configured to execute instructions;
- a device connected to the host processor via a bus and comprising an accelerator circuit and a memory controller;
- and
- a memory configured to be accessed by the accelerator circuit via the memory controller,
- wherein the accelerator circuit is configured to store first data in the memory based on indirect addressing,
- wherein the accelerator circuit is further configured to provide a first read request including an indirect address of the first data stored in the memory, to the memory controller,
- wherein the memory controller is further configured to:
- identify the indirect address of the first data based on first information included in the first read request,
- read a direct address of the first data from a first region of the memory corresponding to the indirect address of the first data,
- provide the direct address to the accelerator circuit in response to the first read request, and
- prefetch the first data from a second region of the memory corresponding to the direct address, and
- wherein the memory controller is further configured to perform the prefetch by providing a second read command to the memory, together with the direct address, without an additional read request issued with respect to the first read request by the accelerator circuit.
A method performed by a device connected to a host processor via a bus, wherein the device comprises an accelerator circuit, the method comprising:
- storing first data in a memory based on indirect addressing
- providing, by the accelerator circuit to the memory, a first read request including a first address;
- receiving, by the accelerator circuit from the memory in response to the first read request, a second address stored in a first region of the memory corresponding to the first address;
- providing, to the memory, a second read request including the second address;
- and
- receiving, from the memory, the first data stored in a second region of the memory corresponding to the second address,
- wherein the first read request further includes first information indicating that the first address is an indirect address of the first data, and
- wherein a second period of time taken from the providing of the second read request to the receiving of the first data is shorter than a first period of time taken from the providing of the first read request to the receiving of the second address.
Dependencies are inferred from the claim text.