Memory controlling device and memory system including the same
AssigneesMemRay Corporation, Yonsei University, University—Industry Foundation (Uif)
InventorsMyoungsoo Jung, Gyuyoung Park, Miryeong Kwon
Life of this patent
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Abstract
A memory controlling device configured to connect to a memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions including a first partition and a second partition is provided. A first controlling module accesses the memory module. A second controlling module determines whether there is a conflict for the first partition to which a read request targets when an incoming request is the read request, instructs the first controlling module to read target data of the read request from the memory module when a write to the second partition is in progress, and suspends the read request when a write to the first partition is in progress.
Claims12
A method for a memory controller, for controlling a first memory module, including a memory cell array partitioned into a plurality of partitions, and a second memory module, used as a cache including a plurality of cache lines, comprising:
- determining, for an incoming first read request for first target data, with lookup logic, whether the first read request is a cache hit or miss;
- determining the first read request is a cache miss;
- determining, for the memory cell array being resistance switching, the first read request targets a first partition for the first target data;
- reading the first target data, when a write is in progress, if the write is to a second partition different from the first partition;
- and
- suspending the reading of the first target data, when the read request is the cache miss and when the write in progress is to the first partition.
A method for a memory controller, for controlling a first memory module, including a memory cell array partitioned into a plurality of partitions, and a second memory module, used as a cache including a plurality of cache lines, comprising:
- determining, with lookup logic, a first write request of a first cache line to the first memory module;
- determining, for the memory cell array being resistance switching, the first write request targets a first partition;
- determining a first read request targets a second partition, of the first memory module, for second target data;
- reading the second target data, when the first write is in progress, if the first partition is different from the second partition;
- and
- suspending the reading of the second target data, when the read request is the cache miss and when the first write in progress, if the first partition is the same as the second partition.
Dependencies are inferred from the claim text.