Jitter noise detector
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorTien-Chien Huang
Life of this patent
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Abstract
A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.
Claims20
A noise detection circuit, comprising:
- a first component configured to receive a clock signal;
- a second component configured to receive a reference clock signal, wherein the first and second components each comprises an n-type metal-oxide-semiconductor (NMOS) field-effect-transistor (FET);
- a latch circuit, coupled to the first component at a first node and coupled to the second component at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on a timing difference between transition edges of the clock signal and the reference clock signal;
- and
- a plurality of capacitors coupled between the first and second nodes.
A noise detection circuit, comprising:
- a first n-type metal-oxide-semiconductor (NMOS) field-effect-transistor (FET) configured to receive a clock signal;
- a second NMOS FET configured to receive a reference clock signal;
- and
- a latch circuit, coupled to the first NMOS FET at a first node and coupled to the second NMOS FET at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on a timing difference between transition edges of the clock signal and the reference clock signal.
A method, comprising:
- receiving a clock signal and a reference clock signal, wherein at least a transition edge of the clock signal is deviated from a transition edge of the reference clock signal by a timing difference;
- receiving the clock signal and reference clock signal by a first transistor and a second transistor, respectively, to start either discharging or charging voltage levels at drains of the first and second transistors at different times;
- and
- latching respective logic states of the voltage levels at the drains of the first and second transistors when the timing difference is greater than a pre-defined timing offset threshold.
Dependencies are inferred from the claim text.