US 11,804,805 B2 · High-speed current-feedback amplifier with distortion cancellation

Abstract

Described examples include an integrated circuit having an input stage with an input and an output. A first current mirror is coupled to the output, the first current mirror including a first transistor having an emitter and a base coupled to the output of the input stage, and a collector coupled to a reference potential. The first current mirror also includes a second transistor having a base coupled to the base of the first transistor, an emitter coupled to the reference potential and a collector coupled to an output node. A buffer has an input coupled to the output node and an output. A third transistor has a base and an emitter coupled to the reference potential and a collector coupled to the output of the buffer. A second current mirror couples a portion of the buffer output current to the base of the first transistor.

Claims20

Dependent claims

An integrated circuit having a voltage input and a current output responsive to the voltage input, the integrated circuit comprising:

an input stage coupled to the voltage input;
a first current mirror coupled to the input stage, the first current mirror including:
a first transistor having:
a first current terminal;
a second current terminal operable to be coupled to a first voltage supply;
and
a control terminal coupled to the input stage and the first current terminal;
a second transistor having:
a control terminal coupled to the control terminal of the first transistor;
a first current terminal operable to be coupled to the first voltage supply;
and
a second current terminal;
a buffer having an input coupled to the second current terminal of the second transistor and having a buffer output;
a third transistor having a control terminal and a first current terminal coupled to the first voltage supply and having a second current terminal coupled to the buffer output;
and
wherein the buffer is operable to output a current to offset a distortion current provided by the first current mirror.

13 more elements

An integrated circuit comprising:

a first transistor having a control terminal coupled to a first input node, a first current terminal coupled to a first input terminal and having a second current terminal;
a second transistor having a control terminal coupled to the first input node, a first current terminal coupled to the second input terminal and having a second current terminal;
a third transistor having a control terminal and a first current terminal coupled to the second current terminal of the first transistor, and the third transistor having a second current terminal coupled to a first reference potential;
a fourth transistor having a control terminal and a first current terminal coupled to the second current terminal of the second transistor, and the fourth transistor having a second current terminal coupled to a second reference potential;
a fifth transistor having a control terminal coupled to the control terminal of the third transistor, a first current terminal coupled to an output node and a second current terminal coupled to the first reference potential;
a sixth transistor having a control terminal coupled to the control terminal of the fourth transistor, a first current terminal coupled to the output node, and a second current terminal coupled to the second reference potential;
a buffer having an input coupled to the output node and having an output;
a seventh transistor having a first current terminal coupled to the output of the buffer, and having a control terminal and a second current terminal coupled to the first reference potential;
and
a current source coupled to the control terminal of the fifth transistor and operable to provide a current that is proportional to a current provided by the buffer through the seventh transistor.

7 more elements

An integrated circuit comprising:

a first transistor having a control terminal coupled to a first input node, a first current terminal coupled to a second input terminal and having a second current terminal;
a second transistor having a control terminal coupled to the first input node, a first current terminal coupled to the second input terminal and having a second current terminal;
a third transistor having a control terminal and a first current terminal coupled to the second current terminal of the first transistor, and the third transistor having a second current terminal coupled to a first reference potential;
a fourth transistor having a control terminal and a first current terminal coupled to the second current terminal of the second transistor, and the fourth transistor having a second current terminal coupled to a second reference potential;
a fifth transistor having a control terminal coupled to the control terminal of the third transistor, a first current terminal coupled to an output node and a second current terminal coupled to the first reference potential;
a sixth transistor having a control terminal coupled to the control terminal of the fourth transistor, a first current terminal coupled to the output node, and a second current terminal coupled to the second reference potential;
a first buffer having an input coupled to the output node and having an output;
a seventh transistor having a first current terminal coupled to the output of the buffer, and having a control terminal and a second current terminal coupled to the first reference potential;
and
a first current source coupled to the control terminal to the fifth transistor and operable to provide a current that is proportional to a current provided by the buffer through the seventh transistor:
a second buffer having an input coupled to the output node and having an output;
an eighth transistor having a first current terminal coupled to the output of the buffer, and having a control terminal and a second current terminal coupled to the second reference potential;
and
a second current source coupled to the control terminal of the sixth transistor and operable to provide a current that is proportional to a current provided by the buffer through the eighth transistor.

11 more elements

Dependencies are inferred from the claim text.

High-speed current-feedback amplifier with distortion cancellation

Life of this patent

High-speed current-feedback amplifier with distortion cancellation

Life of this patent

Abstract

Claims20