Fast triggering electrostatic discharge protection
AssigneeNVIDIA Corporation
InventorsJauwen Chen, Sunitha Venkataraman, Ting Ku
Life of this patent
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Abstract
An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.
Claims6
An electrostatic discharge protection circuit for an IO pad, the electrostatic discharge protection circuit comprising:
- a connection between the IO pad and a circuit ground, the connection consisting of a stacked drain-ballasted NMOS devices structure;
- wherein a channel of each of the NMOS devices is coupled to a channel of a tuning transistor, the channel of the tuning transistor being directly connected to the circuit ground;
- a gate bias circuit comprising:
- an inverter directly connected to a power supply rail at its inverting input terminal;
- a first gate bias output terminal coupled via a series of diodes to the IO pad and to a gate of a first one of the drain-ballasted NMOS devices;
- and
- a second gate bias output terminal from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.
Dependencies are inferred from the claim text.