Floating body dram with reduced access energy
AssigneeRambus Inc.
InventorsFrederick A. Ware, John Eric Linstadt, Zhichao Lu, Kenneth Lee Wright
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Abstract
Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.
Claims20
A buffer device, comprising:
- a primary interface to receive a read command from a memory controller;
- a secondary interface to retransmit the read command to a memory device to access first read data stored in a first group of floating body storage cells of the memory device;
- and
- conditional writeback circuitry coupled to the secondary interface, the conditional writeback circuitry to generate a writeback command for transfer to the memory device, the writeback command generated in response to one of a predetermined probability, a threshold count of a number of accesses to the first group of the floating body storage cells, or a tag value exhibiting a first sense characteristic.
A method of operation in a buffer device, the method comprising:
- receiving read transaction component signals from a memory controller via a primary interface;
- retransmitting the read transaction component signals, via a secondary interface, to a memory device to access first read data stored in a first group of floating body storage cells of the memory device;
- conditionally generating a writeback command with conditional writeback circuitry, the conditional writeback circuitry generating the writeback command in response to one of a predetermined probability, a threshold count of a number of accesses to the first group of the floating body storage cells, or a tag value exhibiting a first sense characteristic.
An integrated circuit (IC) buffer chip, comprising:
- interface circuitry to receive a read command from memory control circuitry, and to retransmit the read command to a memory device to access first read data stored in a first group of floating body storage cells of the memory device;
- and
- conditional writeback circuitry coupled to the interface circuitry, the conditional writeback circuitry to generate a writeback command for transfer to the memory device, the writeback command generated in response to a satisfied event.
Dependencies are inferred from the claim text.