Signal converter device, dynamic element matching circuit, and dynamic element matching method
AssigneeRealtek Semiconductor Corp.
InventorSheng-Hsiung Lin
Life of this patent
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Abstract
A dynamic element method includes the following operations: summing up most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal; outputting the first signal to be an adjusted pointer signal according to a clock signal; and decoding the adjusted pointer signal to be control signals, in which the control signals are configured to set corresponding relations of components of a first digital to analog converter circuits and the most significant bits, in order to utilize the components to convert the most significant bits.
Claims20
A signal converter device, comprising:
- a first digital to analog converter circuit comprising a plurality of components, wherein the first digital to analog converter circuit is configured to utilize the plurality of components to generate a first signal component of a first signal in response to a plurality of first bits;
- a second digital to analog converter circuit configured to generate a second signal component of the first signal in response to a second bit, wherein weights corresponding to the plurality of first bits are higher than a weight corresponding to the second bit;
- and
- a dynamic element matching circuit configured to generate an adjusted pointer signal in response to a pointer signal and the plurality of first bits in a previous period, in order to set corresponding relations between the plurality of components and the plurality of first bits.
A dynamic element matching circuit, comprising:
- an arithmetic logic unit circuit configured to sum up a plurality of most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal;
- a register circuit configured to output the first signal to be an adjusted pointer signal according to a clock signal;
- and
- a decoder circuit configured to decode the adjusted pointer signal to be a plurality of control signals, wherein the plurality of control signals are configured to set corresponding relations of a plurality of components of a first digital to analog converter circuits and the plurality of most significant bits, in order to utilize the plurality of components to convert the plurality of most significant bits.
A dynamic element matching method, comprising:
- summing up a plurality of most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal;
- outputting the first signal to be an adjusted pointer signal according to a clock signal;
- and
- decoding the adjusted pointer signal to be a plurality of control signals,
- wherein the plurality of control signals are configured to set corresponding relations of a plurality of components of a first digital to analog converter circuits and the plurality of most significant bits, in order to utilize the plurality of components to convert the plurality of most significant bits.
Dependencies are inferred from the claim text.