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US 11,797,474 B2Granted
High performance processor
AssigneeHyperion Core, Inc.
InventorMartin Vorbach
Life of this patent
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Abstract
Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.
Claims21
A data processor comprising:
- at least one data processing unit having a plurality of processing elements to process data;
- and
- a data cache hierarchy to cache the data processed by the at least one data processing unit, the data cache hierarchy being part of a memory hierarchy having at least a main memory and the data cache hierarchy hierarchically below the main memory, the data cache hierarchy including as part of the data processor:
- a plurality of levels of data caches, the data caches including at least:
- a lower level data cache;
- a higher level data cache connected to the lower level data cache;
- and
- at least one cache controller for each of the data caches, the at least one cache controller controlling the operation thereof;
- wherein the main memory is connected to at least one of:
- a highest level data cache of the data cache hierarchy or an interface connecting at least the data cache hierarchy to the main memory,
- wherein:
- at least one of the higher level data cache or the lower level data cache is unitarily used as a common cache for the plurality of processing elements during a first period of time,
- the at least one of the higher level data cache or the lower level data cache is divided into a plurality of cache segments,
- at least one processing element of the plurality of processing elements has at least one cache segment of the plurality of cache segments associated therewith for use as its tightly coupled memory during a second period of time;
- and
- the at least one cache controller is adapted to, during operation of the data processor, exclude the at least one cache segment associated with the at least one processing element at least temporarily from cache operation during the second period of time, such that during the second period of time the at least one processing element has access to the at least one cache segment without access control by the at least one cache controller.
13 more elements
A data processor chip comprising
- at least one data processing unit having a plurality of processing elements to process data;
- and
- a data cache hierarchy to cache the data processed by the at least one data processing unit, the data cache hierarchy being part of a memory hierarchy having at least a main memory and the data cache hierarchy hierarchically below the main memory, the data cache hierarchy including as part of the data processor chip:
- a plurality of levels of data caches, the data caches including at least:
- a lower level data cache;
- a higher level data cache connected to the lower level data cache;
- and
- at least one cache controller for each of the data caches, the at least one cache controller controlling the operation thereof;
- wherein the main memory is connected to at least one of:
- a highest level data cache of the data cache hierarchy or an interface connecting at least the data cache hierarchy to the main memory,
- wherein:
- at least one of the higher level data cache or the lower level data cache is unitarily used as a common cache for the plurality of processing elements during a first period of time,
- the at least one of the higher level data cache or the lower level data cache is divided into a plurality of cache segments,
- at least one processing element of the plurality of processing elements has at least one cache segment of the plurality of cache segments associated therewith for use as its tightly coupled memory during a second period of time;
- the at least one cache controller is adapted to, during operation of the data processor chip, exclude the at least one cache segment associated with the at least one processing element at least temporarily from cache operation during the second period of time, such that during the second period of time the at least one processing element has access to the at least one cache segment without access control by the at least one cache controller;
- and
- each of multiple cache segments is associated with a respective processing element as tightly coupled memory and is located physically close to the associated processing element such that the multiple cache segments are spread across the data processor chip.
14 more elements
Dependencies are inferred from the claim text.