Apparatus for calculating and retaining a bound on error during floating-point operations and methods thereof

A method of producing a floating-point result by use of a main processing unit (910) communicably coupled to a bounded floating-point unit (BFPU) (950);

• wherein said BFPU (950) comprises a bounded floating-point addition/subtraction circuit (200);
• and wherein said bounded floating-point addition/subtraction circuit (200) comprises a dominant bound circuit (400), a main bound circuit (600), and multiple registers that accommodate operands in a bounded floating-point format (100);
• wherein said bounded floating-point format (100) comprises a sign bit S Field (50), an exponent E Field (51), a bound B Field (52), and a significand T Field (53);
• wherein said bound field (52) comprises a lost bits D Field (54) and an accumulated rounding error N Field (55);
• and wherein said accumulated rounding error N Field (55) comprises a rounding error count C Field (56) and a rounding bits R Field (57);
• the method comprising:
• receiving, by said BFPU (950) a floating-point arithmetic instruction (930) and a bound limit selection instruction (830, 832);
• calculating, by said BFPU (950), a calculated result (260) value from applying an operation of said floating-point arithmetic instruction (930) on a first operand (201) and a second operand (202);
• calculating, by said BFPU (950), a bounded floating-point result (280);
• and
• detecting if a dominant bound B 52H is zero.