Digital phase-locked loop with fast output frequency digital control

A method for performing polar modulation using a digital phase-locked loop (DPLL) frequency synthesizer comprising:

• providing a DPLL, the DPLL comprising:
• a digitally controlled oscillator (DCO) having an input and an output, the output configured to produce a signal with a frequency;
• a reference oscillator arranged to provide a reference frequency;
• a digital phase detector coupled to the reference oscillator to receive the reference frequency, the digital phase detector arranged to compare a target frequency code (TFC) generated according to the reference frequency with a digital code (FFC) representing the frequency of the output of the DCO to generate a difference signal;
• a DCO control module coupled to the DCO and the digital phase detector, the DCO control module configured to receive the difference signal from the digital phase detector for controlling the frequency of the output of the DCO, the DCO control module comprising a plurality of registers each arranged to control the frequency of the signal with a predetermined resolution, wherein the plurality of registers comprise a first register for precise frequency control and a second register for fine frequency control, wherein the frequency of the output of the DCO is tracked by changing a value of the first register and a value of the second register defines a tracking range for tracking the frequency of the output of the DCO;
• a first feedback loop arranged to provide a first feedback path between the output of the DCO and the digital phase detector;
• and
• a second feedback loop arranged to provide a second feedback path between the first register output and the second register for changing the tracking range by changing the value of the second register based on the value of the first register;
• providing a polar encoder and operatively connecting the polar encoder to the one of the plurality of registers to directly control the frequency of the output of the DCO based on a symbol processed by for polar encoding;
• and
• operatively connecting the polar encoder to the digital phase detector to provide the digital phase detector with a target frequency corresponding to the symbol, wherein the target frequency code (TFC) is generated from the target frequency according to the reference frequency.