Semiconductor package including semiconductor chips
AssigneeSamsung Electronics Co., Ltd.
InventorsHyungu Kang, Jaekyu Sung
Life of this patent
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Abstract
A semiconductor package may include a semiconductor chip on a package substrate. The semiconductor package may include a plurality of conductive connections connecting the semiconductor chip to the package substrate may be disposed, a plurality of towers which are apart from one another and each include a plurality of memory chips may be disposed, wherein a lowermost memory chip of each of the plurality of towers overlaps the semiconductor chip from a top-down view. The semiconductor package further includes a plurality of adhesive layers be attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip.
Claims20
A semiconductor package comprising:
- a package substrate;
- a semiconductor chip on the package substrate;
- a plurality of first conductive connections connecting the semiconductor chip to the package substrate;
- a first spacer and a second spacer on the package substrate, each of the first spacer and the second spacer horizontally spaced apart from the semiconductor chip;
- a first tower and a second tower each including a plurality of memory chips, a first memory chip disposed at a lowermost end of the first tower and vertically overlapping the semiconductor chip and the first spacer from a top-down view, and a second memory chip disposed at a lowermost end of the second tower and vertically overlapping the semiconductor chip and the second spacer from a top-down view;
- and
- a plurality of first adhesive layers including an adhesive layer covering a lower surface of the first memory chip and partially covering an upper surface of the semiconductor chip and an adhesive layer covering a lower surface of the second memory chip and partially covering the upper surface of the semiconductor chip.
A semiconductor package comprising:
- a package substrate including a plurality of substrate pads;
- a semiconductor chip on the package substrate and including a plurality of pads;
- a plurality of first conductive connections connecting the semiconductor chip to the package substrate;
- a plurality of towers apart from one another, each including a plurality of memory chips, a lowermost memory chip of each of the plurality of towers overlapping the semiconductor chip from a top-down view;
- and
- a plurality of adhesive layers attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip,
- wherein at least one of the plurality of pads are connected to one of the plurality of memory chips and at least one of the plurality of pads are connected to the package substrate.
A semiconductor package comprising:
- a package substrate including a plurality of substrate pads;
- a semiconductor chip on the package substrate and including a plurality of pads;
- a plurality of conductive connections connecting the semiconductor chip to the package substrate;
- a first tower and a second tower each including a plurality of memory chips, a lowermost memory chip of each of the first and second towers overlapping the semiconductor chip from a top-down view;
- and
- a plurality of adhesive layers respectively attached between the lowermost memory chip of the first and second towers and the semiconductor chip,
- wherein the plurality of pads includes a plurality of first pads connected to the first tower and a plurality of second pads connected to the second tower, and
- wherein at least one of the plurality of first pads are disposed adjacent to at least one of the plurality of second pads.
Dependencies are inferred from the claim text.