Memory devices for performing repair operation, memory systems including the same, and operating methods thereof
AssigneeSamsung Electronics Co., Ltd.
InventorYongsang Park
Life of this patent
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Abstract
A memory device includes a mode register set configured to store a first repair mode, a second repair mode, and a second repair off mode, and a repair control circuit configured to perform a first repair operation for permanently repairing a first wordline corresponding to a defective address to a first redundancy wordline in the first repair mode, to perform a second repair operation for temporarily repairing the first wordline corresponding to the defective address to a second redundancy wordline in the second repair mode, and to turn off a repair logic that is configured to perform the second repair operation in the second repair off mode to access old data after the second repair operation.
Claims20
A memory device comprising:
- a normal wordline activation logic circuit configured to output a normal wordline activation signal in response to an active row address being matched;
- a first redundancy circuit configured to output a post package repair (PPR) wordline activation signal and activate a PPR wordline in response to the active row address being matched;
- and
- at least one second redundancy circuit configured to output a soft post package repair (sPPR) wordline activation signal and activate a sPPR wordline in response to the active row address being matched,
- wherein the at least one second redundancy circuit is inactivated and the sPPR wordline is not activated in response to the at least one second redundancy circuit receiving old data access information.
An operating method of a memory device, the method comprising:
- outputting a normal wordline activation signal by a normal wordline activation logic circuit, in response to an active row address being matched;
- outputting a post package repair (PPR) wordline activation signal and activating a PPR wordline by one of a plurality of first redundancy circuits in response to the active row address being matched;
- outputting a soft post package repair (sPPR) wordline activation signal by a second redundancy circuit and activating a sPPR wordline in response to the active row address being matched;
- and
- activating a corresponding wordline in response to one of the normal wordline activation signal, the PPR wordline activation signal, or the sPPR wordline activation signal,
- wherein the second redundancy circuit is inactivated and the sPPR wordline is not activated in response to the second redundancy circuit receiving old data access information.
A memory system comprising:
- at least one memory device;
- and
- a memory controller configured to control the at least one memory device, wherein the at least one memory device includes:
- a memory cell array having a plurality of banks, each of the banks being a plurality of memory cells electrically connected between wordlines and bitlines;
- a normal wordline activation logic circuit configured to output a normal wordline activation signal in response to an active row address being matched;
- first redundancy circuits configured to output a post package repair (PPR) wordline activation signal and activate a PPR wordline in response to the active row address being matched;
- and
- at least one second redundancy circuit configured to output a soft post package repair (sPPR) wordline activation signal and activate a sPPR wordline in response to the active row address being matched,
- wherein the at least one second redundancy circuit is inactivated and the sPPR wordline is not activated in response to the at least one second redundancy circuit receiving old data access information.
Dependencies are inferred from the claim text.