US 11,789,734 B2 · Padded vectorization with compile time known masks

Abstract

A computing system includes a processing unit and a memory storing instructions that, when executed by the processor, cause the processor to receive program source code in a compiler, identify in the program source code a set of operations for vectorizing, where each operation in the set of operations specifies a set of one or more operands, in response to identifying the set of operations, vectorize the set of operations by, based on the number of operations in the set of operations and a total number of lanes in a first vector register, generating a mask indicating a first unmasked lane and a first masked lane in the first vector register, based on the mask, generating a set of one or more instructions for loading into the first unmasked lane a first operand of a first operation of the set of operations, and loading the first operand into the first masked lane.

Claims16

Dependent claims

A computing system, comprising:

a processing unit;
and
a memory storing a set of instructions that, when executed by the processing unit, cause the processing unit to:
vectorize a set of operations in a program source code received at a compiler, including:
based on a mask indicating a first unmasked lane and a first masked lane in a first vector register and a second unmasked lane and a second masked lane in a second vector register, generating one or more instructions for loading a first operand of a first operation of the set of operations into the first unmasked lane and into the first masked lane, and loading a second operand of the first operation of the set of operations into the second unmasked lane and into the second masked lane;
and
generating a single instruction, multiple data (SIMD) instruction for performing the first operation on the first operand in the first unmasked lane and the second operand in the second unmasked lane in parallel with performing the first operation on the first operand in the first masked lane and the second operand in the second masked lane.

4 more elements

A non-transitory computer readable storage medium storing instructions for a compiler, wherein the instructions are executable by a processor to:

vectorize a set of operations in a program source code, including:
in response to receiving program source code at a compiler and based on a mask indicating a first unmasked lane and a first masked lane in a first vector register and a second unmasked lane and a second masked lane in a second vector register, generate one or more instructions for loading a first operand of a first operation of the set of operations into the first unmasked lane and into the first masked lane, and loading a second operand of the first operation of the set of operations into the second unmasked lane and into the second masked lane;
and
generating a single instruction, multiple data (SIMD) instruction for performing the first operation on the first operand in the first unmasked lane and the second operand in the second unmasked lane in parallel with performing the first operation on the first operand in the first masked lane and the second operand in the second masked lane.

1 more element

Dependencies are inferred from the claim text.

Padded vectorization with compile time known masks

Life of this patent

Padded vectorization with compile time known masks

Life of this patent

Abstract

Claims16