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US 11,785,759 B2Granted
Floating body memory cell having gates favoring different conductivity type regions
AssigneeIntel Corporation
InventorsPeter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
Life of this patent
Estimating the term…
Abstract
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
Claims25
An integrated circuit structure, comprising:
- a semiconductor fin on a substrate, the semiconductor fin having a top surface and a longest direction;
- a first gate structure on a first side of the semiconductor fin, the first gate structure having a top surface and a longest direction, the top surface of the first gate structure above the top surface of the semiconductor fin with respect to the substrate, and the longest direction of the first gate structure orthogonal to the longest direction of the semiconductor fin, the first gate structure comprising a first gate dielectric and a first gate electrode;
- and
- a second gate structure on a second side of the semiconductor fin, the second side opposite the first side, the second gate structure having a top surface and a longest direction, the top surface of the second gate structure above the top surface of the semiconductor fin with respect to the substrate, and the longest direction of the second gate structure orthogonal to the longest direction of the semiconductor fin and parallel with the longest direction of the first gate structure, the second gate structure comprising a second gate dielectric and a second gate electrode, wherein the second gate electrode has a work function different than a workfunction of the first gate electrode.
1 more element
An integrated circuit structure, comprising:
- a semiconductor fin on a substrate, the semiconductor fin having a top surface and a longest direction;
- a first gate structure on a first side of the semiconductor fin, the first gate structure having a top surface and a longest direction, the top surface of the first gate structure above the top surface of the semiconductor fin with respect to the substrate, and the longest direction of the first gate structure orthogonal to the longest direction of the semiconductor fin, the first gate structure comprising a first gate dielectric and a first gate electrode, the first gate dielectric having a first thickness and a first composition;
- and
- a second gate structure on a second side of the semiconductor fin, the second side opposite the first side, the second gate structure having a top surface and a longest direction, the top surface of the second gate structure above the top surface of the semiconductor fin with respect to the substrate, and the longest direction of the second gate structure orthogonal to the longest direction of the semiconductor fin and parallel with the longest direction of the first gate structure, the second gate structure comprising a second gate dielectric and a second gate electrode, wherein the second gate dielectric has a second thickness and a second composition, wherein at least one of the second thickness is different than the first thickness or the second composition is different than the first composition.
1 more element
Dependencies are inferred from the claim text.