High gain detector techniques for high bandwidth low noise phase-locked loops

A phase locked loop (PLL) comprising:

• a first phase detector (PD) having first PD inputs and a first PD output, the first PD inputs coupled to a reference input and a clock input;
• a second PD having second PD inputs and a second PD output, the second PD inputs coupled to the reference input and the clock input;
• an amplifier having a positive amplifier input, a negative amplifier input, and an amplifier output, the positive amplifier input coupled to the first PD output, the negative amplifier input coupled to the second PD output, and the amplifier output coupled to a control output;
• a third PD having third PD inputs and a third PD output, the third PD inputs coupled to the reference input and the clock input;
• a capacitor coupled between the third PD output and the control output;
• and
• a voltage-controlled oscillator (VCO) having a control input and a VCO output, the control input being coupled to the control output, and the VCO output coupled to the clock input.