Controller to detect malfunctioning address of memory device
AssigneeRambus Inc.
InventorsAdrian E. Ong, Fan Ho
Life of this patent
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Abstract
A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.
Claims18
A dynamic random access memory (DRAM) comprising:
- a plurality of primary data storage elements;
- a plurality of redundant data storage elements;
- and
- circuitry to:
- receive a first register setting command;
- initiate a repair mode in the DRAM in response to the first register setting command;
- receive an activation command;
- in response to receiving the activation command, repair a malfunctioning row address in the DRAM receive a precharge command;
- receive a second register setting command;
- terminate the repair mode in the DRAM in response to the second register setting command;
- receive a memory access request for data stored at the malfunctioning row address;
- and
- redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.
A dynamic random access memory (DRAM) comprising:
- a plurality of primary data storage elements;
- a plurality of redundant data storage elements;
- and
- circuitry to:
- receive a first register setting command;
- initiate a repair mode in the DRAM in response to the first register setting command;
- receive an activation command, the activation command comprising an indication of a malfunctioning row address in the DRAM to be repaired;
- in response to receiving the activation command, repair the malfunctioning row address in the DRAM;
- store, in one or more registers, the indication of the malfunctioning row address;
- receive a precharge command;
- receive a second register setting command;
- terminate the repair mode in the DRAM in response to the second register setting command;
- receive a memory access request for data stored at the malfunctioning row address;
- and
- redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.
A controller comprising:
- an internal memory to store a row address for repair;
- and
- a memory control unit operatively coupled with the internal memory, the memory control unit comprising logic to:
- transmit a first register setting command to initiate a row repair mode in an external memory device, wherein the controller is a first semiconductor device, and wherein the external memory device is a second semiconductor device that is separate from the first semiconductor device;
- transmit an activation command comprising an indication of the row address for repair, wherein the indication is stored in the internal memory of the controller;
- transmit a precharge command;
- and
- transmit a second register setting command to terminate the row repair mode in the external memory device.
Dependencies are inferred from the claim text.