Arithmetic logic unit, multiply-accumulate operation device, multiply-accumulate operation circuit, and multiply-accumulate operation system

A multiply-accumulate operation device, comprising:

• a pair of output lines;
• a plurality of multiplication units each that includes a weight unit that generates, on a basis of electrical signals input to a plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on a basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines;
• an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units;
• and
• an output unit that outputs, on a basis of the accumulated charges, a multiply-accumulate signal representing a sum of the multiplication values.

A multiply-accumulate operation circuit, comprising:

• a pair of output lines;
• a plurality of multiplication units each that includes a weight unit that generates, on a basis of electrical signals input to a plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on a basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines;
• an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units;
• and
• an output unit that outputs, on a basis of the accumulated charges, a multiply-accumulate signal representing a sum of the multiplication values.

A multiply-accumulate operation system, comprising:

• a plurality of input lines, electrical signals being input to the plurality of input lines;
• a plurality of analog circuits that includes a pair of output lines, a plurality of multiplication units each including a weight unit that generates, on a basis of the electrical signals input to the plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on a basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines, an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units, and an output unit that outputs, on a basis of the accumulated charges, a multiply-accumulate signal representing a sum of the multiplication values;
• and
• a network circuit configured by connecting the plurality of analog circuits.