Diffusion barrier layer in programmable metallization cell

A method for forming an integrated chip, comprising:

• forming a bottom electrode via over a substrate;
• forming a memory cell layer stack over the bottom electrode via, wherein the memory cell layer stack comprises a bottom electrode, a data storage layer over the bottom electrode, a diffusion barrier layer over the data storage layer, and a top electrode over the diffusion barrier layer, wherein a first conductive material of the diffusion barrier layer is different from a second conductive material of the top electrode, and wherein a conductive bridge is formable and dissolvable within a middle region of the data storage layer;
• and
• etching the memory cell layer stack to define a memory cell over the bottom electrode via.

A method for forming a memory device, the method comprising:

• forming a lower conductive wire over a substrate;
• forming a bottom electrode via over the lower conductive wire;
• forming a memory cell layer stack over the bottom electrode via, wherein the memory cell layer stack includes a bottom electrode, a data storage layer, a diffusion barrier layer, and a top electrode, wherein the diffusion barrier layer is disposed between the data storage layer and the top electrode, wherein the top electrode comprises a diffusive species, and wherein the diffusion barrier layer is configured to block diffusion of the diffusive species;
• and
• patterning the memory cell layer stack, thereby defining a programmable metallization cell.