Method of fabricating a vertical semiconductor device

A method of fabricating a vertical semiconductor device, the method comprising:

• forming a lower sacrificial layer pattern on a substrate;
• forming a support layer on the lower sacrificial layer pattern;
• alternately stacking a sacrificial layer and an insulating layer on the support layer;
• forming a channel hole penetrating the sacrificial layer, the insulating layer, the support layer, and a lower sacrificial layer pattern;
• partially removing an exposed sidewall of the support layer in the channel hole;
• forming an information storage material layer and a channel pattern in the channel hole;
• forming a word line cut opening penetrating the sacrificial layer, the insulating layer, and the support layer;
• selectively removing the lower sacrificial layer pattern through the word line cut opening;
• removing a portion of the information storage material layer exposed by removing the lower sacrificial layer pattern;
• forming a common source semiconductor layer in contact with the channel pattern;
• and
• replacing the sacrificial layer with gates.

A method of fabricating a vertical semiconductor device, the method comprising:

• forming a lower sacrificial layer pattern on a well of a first conductivity type of a substrate having a second conductivity type;
• forming a support layer on the lower sacrificial layer pattern;
• alternately stacking a sacrificial layer and an insulating layer on the support layer;
• forming a channel hole penetrating the sacrificial layer, the insulating layer, the support layer, and a lower sacrificial layer pattern;
• partially removing an exposed sidewall of the support layer in the channel hole so that the sidewall of the support layer is offset relative to a side wall of the sacrificial layer;
• forming an information storage material layer and a channel pattern in the channel hole so that the information storage material layer and the channel pattern fill a space formed by partially removing the exposed sidewall of the support layer in the channel hole;
• forming a word line cut opening penetrating the sacrificial layer, the insulating layer, and the support layer;
• forming a spacer to cover a sidewall of the word line cut opening;
• selectively removing the lower sacrificial layer pattern through the word line cut opening;
• removing a portion of the information storage material layer exposed by selectively removing the lower sacrificial layer pattern;
• forming a common source semiconductor layer in contact with the channel pattern;
• and
• replacing the sacrificial layer with gates,
• wherein the channel pattern includes a channel pattern extension portion protruding toward the support layer in the horizontal direction of the support layer.