Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Han Lin, Te-An Chen
Life of this patent
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Abstract
In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
Claims20
A semiconductor device including:
- a non-volatile memory cell formed in a memory cell area of a substrate;
- a first circuit formed in a first circuit area of the substrate;
- and
- an isolation insulating layer disposed between the memory cell area and the first circuit area, wherein:
- an upper surface of the isolation insulating layer comprises four horizontal surfaces having different vertical levels,
- the four horizontal surfaces include a top surface, a first middle surface lower than the top surface, a second middle surface lower than the first middle surface and a bottom surface lower than the second middle surface, and
- the top surface, the first middle surface, the second middle surface and the bottom surface are arranged in this order from the first circuit.
A semiconductor device including:
- a non-volatile memory cell formed in a memory cell area of a substrate;
- a first circuit formed in a first circuit area of the substrate;
- and
- an isolation insulating layer disposed between the memory cell area and the first circuit area, wherein:
- an upper surface of the isolation insulating layer comprises horizontal surfaces including a top surface, a middle surface lower than the top surface and a bottom surface lower than the middle surface,
- the top surface and the middle surface are connected by a slope and a first step,
- the middle surface and the bottom surface are connected by a second step, and
- a horizontal length of the bottom surface is longer than a horizontal length of the middle surface.
A method of manufacturing a semiconductor device, the method comprising:
- forming a trench in a substrate at a transition area between a memory cell area and a circuit area;
- forming an isolation insulating layer by filling the trench with an insulating material, the isolation insulating layer including an upper surface having a slope disposed between a top portion and a bottom portion;
- forming at least two steps on the upper surface of the isolation insulating layer between the top portion and the bottom portion;
- and
- forming one or more dielectric layers and a polysilicon layer over an entirety of an upper surface of the isolation insulating layer.
Dependencies are inferred from the claim text.