One-time programmable memory device
AssigneeUnited Microelectronics Corp.
InventorsKuo-Hsing Lee, Chun-Hsien Lin, Sheng-Yuan Hsueh
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Abstract
A semiconductor device includes a substrate having an input/output (I/O) region, an one time programmable (OTP) capacitor region, and a core region, a first metal gate disposed on the I/O region, a second metal gate disposed on the core region, and a third metal gate disposed on the OTP capacitor region. Preferably, the first metal gate includes a first high-k dielectric layer, the second metal gate includes a second high-k dielectric layer, and the first high-k dielectric layer and the second high-k dielectric layer include an I-shape.
Claims12
A semiconductor device, comprising:
- a substrate having an input/output (I/O) region, a core region, and an one time programmable (OTP) capacitor region;
- a first metal gate on the I/O region, wherein the first metal gate comprises a first high-k dielectric layer;
- a second metal gate on the core region, wherein the second metal gate comprises a second high-k dielectric layer and the first high-k dielectric layer and the second high-k dielectric layer comprise an I-shape;
- a third metal gate on the OTP capacitor region, wherein a bottom surface of the first metal gate, a bottom surface of the second metal gate and a bottom surface of the third metal gate are aligned with each other;
- and
- a fourth metal gate on the OTP capacitor region and disposed beside the third metal gate, wherein a portion of the fourth metal gate disposed on a shallow trench isolation which is disposed in the substrate, and the other portion of the fourth metal gate disposed on a doped region.
A semiconductor device, comprising:
- a substrate having an input/output (I/O) region, a core region, and an one time programmable (OTP) capacitor region;
- a first metal gate on the I/O region, wherein the first metal gate comprises a first high-k dielectric layer;
- a second metal gate on the core region, wherein the second metal gate comprises a second high-k dielectric layer and the first high-k dielectric layer and the second high-k dielectric layer comprise a U-shape;
- a third metal gate on the OTP capacitor region, wherein a bottom surface of the first metal gate, a bottom surface of the second metal gate and a bottom surface of the third metal gate are aligned with each other;
- and
- a fourth metal gate on the OTP capacitor region and disposed beside the third metal gate, wherein a portion of the fourth metal gate disposed on a shallow trench isolation which is disposed in the substrate, and the other portion of the fourth metal gate disposed on a doped region.
Dependencies are inferred from the claim text.