Semiconductor memory device and method of fabricating the same

A method of fabricating a semiconductor memory device, the method comprising:

• forming word lines extending in a first direction in a semiconductor substrate;
• forming bit line structures extending in a second direction, each of the bit line structures comprising a conductive pattern, and a hard mask pattern on the conductive pattern;
• forming spacer structures on sidewalls of each of the bit line structures, each of the spacer structures comprising first and second spacers and an air gap between the first and second spacers;
• forming insulating patterns spaced apart from each other between adjacent ones of the bit line structures to define a contact hole between adjacent ones of the insulating patterns and between the adjacent ones of the bit line structures;
• forming a lower landing pad on a lateral surface of the second spacer in the contact hole;
• forming an interlayer dielectric layer on the bit line structures, the insulating patterns, and the lower landing pad;
• patterning the interlayer dielectric layer to form an isolation trench exposing a portion of the lower landing pad and a portion of the spacer structures;
• and
• forming an upper landing pad in the isolation trench.

A method of fabricating a semiconductor memory device, the method comprising:

• forming a bit line structure on a substrate;
• forming a first spacer, a sacrificial spacer, and a second spacer, the first spacer, the sacrificial spacer, and the second spacer sequentially covering a sidewall of the bit line structure;
• forming a lower landing pad on a lateral surface of the second spacer;
• removing the sacrificial spacer to form an air gap between the first spacer and the second spacer;
• forming an interlayer dielectric layer on the bit line structure and the lower landing pad, the interlayer dielectric layer filling an upper portion of the air gap;
• and
• forming an upper landing pad that penetrates the interlayer dielectric layer, the upper landing pad coupled to the lower landing pad,
• wherein the upper landing pad has a bottom surface at a level lower than a top surface of the lower landing pad.