Semiconductor device

A semiconductor device comprising:

• a substrate including isolation films and active regions defined by the isolation films, the active regions being arranged in a first direction;
• a plurality of buried contacts connected to the active regions and arranged in a second direction, the second direction different from the first direction,
• the plurality of buried contacts including first portions and second portions on the first portions,
• the first portions being depressed into the isolation films and the active regions,
• the second portions having a smaller width than top surfaces of the first portions, and having a pillar shape,
• a width of the first portions decreasing away from a top surface of the substrate;
• a plurality of bitline structures between the plurality of buried contacts and extending in a third direction across the active regions, the third direction intersecting the second direction,
• the plurality of bitline structures including first bitline structures overlapping the active regions and second bitline structures overlapping the isolation films,
• the first bitline structures and the second bitline structures being arranged such that the first portions of the plurality of buried contacts are between the first bitline structures and the second bitline structure;
• direct contacts;
• and
• spacer structures extending in the third direction along side surfaces of plurality of bitline structures,
• the spacer structures including first spacers, the first spacers including silicon oxide, the first spacers being at outermost parts of the spacer structures and extending along side surfaces of the second portions of the plurality of buried contacts, wherein
• the spacer structures include first spacer structures on side surfaces of the first bitline structures and second spacer structures on side surfaces of the second bitline structures,
• the first spacer structures are on the first portions of the buried contacts,
• the second spacer structures are spaced apart from the first spacer structures by the second portions of the buried contacts,
• the substrate further includes trenches formed in the isolation films and the active regions,
• the direct contacts are in the trenches,
• a width of the direct contacts is smaller than a width of the trenches in the second direction,
• the spacer structures further include second spacers extending along side surfaces of the first bitline structures, side surfaces of the direct contacts, the trenches and along side surfaces of the second bitline structures,
• the spacer structures further include third spacers between the first spacers and the second spacers,
• at least parts of the first portions of the buried contacts are between the first spacers and second spacers that extend along the trenches, and
• the second spacers and the third spacers include silicon oxide.

A semiconductor device comprising:

• a substrate including gate trenches;
• gate electrodes filling parts of the gate trenches and extending in a first direction;
• source/drain regions on side surfaces of the gate electrodes;
• buried contacts electrically connected to the source/drain regions and arranged in the first direction, the buried contacts including first portions and second portions, and
• in a cross-sectional view taken along the first direction, the first portions being depressed into the substrate and having a semielliptical shape that bulges toward the substrate, and the second portions having a pillar shape with a smaller width than top surfaces of the first portions;
• landing pads on the buried contacts;
• a capacitor structure on the landing pads and electrically connected to the landing pads and the buried contacts;
• bitline structures extending in a second direction between the buried contacts, the second direction intersecting the first direction, the bitline structures being spaced apart from one another in the first direction, and the bitline structures including conductive patterns and capping patterns on the conductive patterns;
• and
• spacer structures on side surfaces of the bitline structures, the spacer structures extending in the second direction,
• the spacer structures including first spacers and second spacers including silicon oxide,
• the second portions of the buried contacts being spaced apart from the bitline structures by the spacer structures,
• the first spacers contacting the second portions of the buried contacts,
• the second spacers contacting the side surfaces of the bitline structures, and
• boundaries between the first portions and the second portions of the buried contacts being coplanar with bottom surfaces of the first spacers.