US 11,778,808 B2Granted

Semiconductor memory device

AssigneeKioxia Corporation

InventorsTeruhisa Sonohara, Shunichi Seno, Hiroki Tokuhira, Fumitaka Arai

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Abstract

A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

Claims17

Dependent claims

A semiconductor memory device comprising:

a first wiring extending in a first direction;
a first semiconductor layer connected to the first wiring, the first semiconductor layer extending in a second direction intersecting with the first direction;
a first electrode extending in a third direction intersecting with the first direction and the second direction, the first electrode being connected to the first semiconductor layer;
a second electrode disposed between the first electrode and the first wiring, the second electrode extending in the third direction and being opposed to the first semiconductor layer;
a third electrode disposed between the second electrode and the first wiring, the third electrode extending in the third direction;
a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode;
and
an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

5 more elements

A semiconductor memory device comprising:

a first wiring extending in a first direction;
a first semiconductor layer connected to the first wiring, the first semiconductor layer extending in a second direction intersecting with the first direction;
a first electrode extending in a third direction intersecting with the first direction and the second direction, the first electrode being connected to the first semiconductor layer;
a second electrode disposed between the first electrode and the first wiring, the second electrode extending in the third direction and being opposed to the first semiconductor layer;
a third electrode arranged with the first electrode via the first semiconductor layer in the first direction, the third electrode extending in the third direction;
a second semiconductor layer disposed between the third electrode and the first semiconductor layer and being opposed to the third electrode;
and
a first electric charge accumulating layer electrically connected to the first electrode via the second semiconductor layer, the first electric charge accumulating layer being opposed to the first semiconductor layer.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/472,902Filed 13 Sep 2021
Priority: JP 2021-0644765 Apr 2021
Published: US 2022/0328489 A113 Oct 2022
Granted: 3 Oct 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

G11C 11/405
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with three charge-transfer gates, e.g. MOS transistors,…
H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
G11C 11/40615
Management or control of the refreshing or charge-regeneration cycles: internal triggering or timing of refresh, e.g. hidden refresh, self…
G11C 11/4076
For memory cells of the field-effect type: timing circuits