Memory device having 2-transistor vertical memory cell and separate read and write gates

An apparatus comprising:

• a data line;
• a conductive region;
• a first transistor included in a memory cell, the first transistor including a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate;
• and
• a second transistor included in the memory cell, the second transistor including a second channel region coupled to the data line and the charge storage structure, and a second gate, wherein the first gate is electrically separated from the second gate, and the first gate is opposite from the second gate in a direction from the first channel region to the second channel region, wherein the data line has a length in the direction from the first channel region to the second channel region.

An apparatus comprising:

• a data line having length in a first direction;
• a first memory cell including:
• a first transistor including a first channel region coupled to the data line, and a first charge storage structure;
• a second transistor including a second channel region coupled to the data line and the first charge storage structure;
• and
• a first dielectric structure having a first side, and a second side opposite from the first side in the first direction, wherein the first channel region is located on the first side of the first dielectric structure, and the second channel region is located on the second side of the first dielectric structure;
• a second memory cell including:
• a third transistor including a third channel region coupled to the data line, and a second charge storage structure;
• a fourth transistor including a fourth channel region coupled to the data line and the second charge storage structure;
• and
• a second dielectric structure having a first side, and a second side opposite from the first side in the first direction, wherein the third channel region is located on the first side of the second dielectric structure, and the fourth channel region is located on the second side of the second dielectric structure;
• a first conductive line forming a first gate of the first transistor;
• a second conductive line forming a second gate of the second transistor;
• a third conductive line forming a third gate of the third transistor;
• and
• a fourth conductive line forming a fourth gate of the fourth transistor, wherein each of the first, second, third, and fourth conductive lines has a length in a second direction.

An apparatus comprising:

• a data line;
• a conductive region;
• a first transistor included in a memory cell, the first transistor including a first channel region coupled to the data line and the conductive region, a charge storage structure, a first dielectric portion between the first charge storage structure and the first channel region, and a first gate;
• and
• a second transistor included in the memory cell, the second transistor including a second channel region coupled to the data line and the charge storage structure, a second dielectric portion between the charge storage structure and the conductive region, and a second gate, wherein the first gate is electrically separated from the second gate, and the first gate is opposite from the second gate in a direction from the first channel region to the second channel region.