Capacitor array structure and fabrication method thereof
AssigneeChangxin Memory Technologies, Inc.
InventorShuai Guo
Life of this patent
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Abstract
Embodiments disclose a capacitor array structure and a method for fabricating a capacitor array structure. The method includes: after forming a first capacitor hole, providing a bonded wafer including a second substrate, a second supporting layer and a second sacrificial layer stacked in sequence, and bonding the bonded wafer to a stacked structure, wherein a surface of the second sacrificial layer away from the second supporting layer is a bonding surface; forming a second capacitor hole, the second capacitor hole penetrating into the bonded wafer at least along a thickness direction to expose the first capacitor hole, such that the first capacitor hole is connected with the second capacitor hole.
Claims15
A capacitor array structure, comprising:
- a semiconductor structure;
- a plurality of first supporting layers arranged in parallel at intervals on the semiconductor structure;
- a first capacitor hole, the first capacitor hole penetrating into each of the plurality of first supporting layers at least along a thickness direction to expose the semiconductor structure;
- a second supporting layer, bonded to the semiconductor structure, a spacing being provided between the second supporting layer and one of the plurality of first supporting layers positioned on a top layer;
- a third supporting layer, positioned on the second supporting layer, a spacing being provided between the third supporting layer and the second supporting layer;
- a second capacitor hole, correspondingly arranged with respect to the first capacitor hole, the second capacitor hole penetrating into the third supporting layer and the second supporting layer at least along the thickness direction to connect with the first capacitor hole;
- a first electrode layer, covering a sidewall of the first capacitor hole, a bottom of the first capacitor hole, and a sidewall of the second capacitor hole;
- a capacitor dielectric layer, covering a surface of the first electrode layer;
- and
- a second electrode layer, covering a surface of the capacitor dielectric layer.
A method for fabricating a capacitor array structure, comprising:
- providing a semiconductor structure;
- forming, on the semiconductor structure, a stacked structure comprising a first sacrificial layer and a first supporting layer alternately stacked from up to down;
- forming a first capacitor hole, the first capacitor hole penetrating into the stacked structure at least along a thickness direction;
- providing a bonded wafer comprising a second substrate, a second supporting layer and a second sacrificial layer stacked in sequence;
- bonding the bonded wafer to the stacked structure, wherein a surface of the second sacrificial layer keeping away from the second supporting layer is a bonding surface;
- forming a third supporting layer on a surface of the second substrate keeping away from the second supporting layer;
- forming a second capacitor hole, the second capacitor hole penetrating into the bonded wafer at least along the thickness direction to connect with the first capacitor hole;
- forming a first electrode layer on a sidewall of the first capacitor hole, a bottom of the first capacitor hole and a sidewall of the second capacitor hole;
- sequentially removing the second substrate, the second sacrificial layer, and the first sacrificial layer;
- forming a capacitor dielectric layer on a surface of the first electrode layer;
- and
- forming a second electrode layer on a surface of the capacitor dielectric layer.
Dependencies are inferred from the claim text.