Cross FET SRAM cell layout
AssigneeAdvanced Micro Devices, Inc.
InventorRichard T. Schultz
Life of this patent
Estimating the term…
Abstract
A system and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. The memory bit cell includes one of a read bit line and a write word line routed in no other metal layer other than a local interconnect layer. In addition, a six transistor (6T) random access data storage of the given memory bit cell consumes a planar area above a silicon substrate of four transistors.
Claims20
An integrated circuit comprising:
- an array of memory bit cells for storing data arranged as a plurality of rows and a plurality of columns, wherein a given memory bit cell of the array comprises a transistor stack that comprises a first transistor with a channel oriented in a first direction and a second transistor with a channel oriented in a direction orthogonal to the first direction;
- wherein in response to receiving an indication of a first read operation targeting a row of the plurality of rows comprising the given memory bit cell, the array conveys data stored in the given memory bit cell to a read bit line.
A method comprising:
- forming a transistor stack in a given memory bit cell, wherein the transistor stack comprises:
- a first transistor with a channel oriented in a first direction;
- and
- a second transistor with a channel oriented in a direction orthogonal to the first direction;
- and
- forming an array of memory bit cells including the given memory bit cell.
A computing system comprising:
- a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks;
- an integrated circuit coupled to communicate with the memory via an interface, wherein the integrated circuit is configured to store a copy of data retrieved from the memory in an array of memory bit cells and execute the instructions using the source data, wherein the array of memory bit cells comprises:
- a plurality of rows and a plurality of columns, wherein a given memory bit cell of the array comprises a transistor stack that comprises a first transistor with a channel oriented in a first direction and a second transistor with a channel oriented in a direction orthogonal to the first direction.
Dependencies are inferred from the claim text.