Gate driving unit, gate driving method, gate driving circuit and display device

A gate driving unit, comprising an input terminal, a latch node control circuit, a first node potential maintenance circuit, and a latch node reset circuit, wherein

• the latch node control circuit is respectively connected to a latch node, the input terminal, and a latch charging terminal, and is configured to control a voltage of the latch node through a charging voltage inputted by the latch charging terminal under the control of an input signal provided by the input terminal,
• the first node potential maintenance circuit is respectively connected to the latch node, a first node, and a latch enable terminal, and is configured to control the connection between the first node and the latch enable terminal under the control of a voltage of the latch node, to maintain a potential of the first node;
• and
• the latch node reset circuit is respectively connected to a latch node reset terminal and the latch node, and is configured to control to reset the potential of the latch node under the control of the latch node reset signal inputted by the latch node reset terminal,
• wherein the gate driving unit further includes a first node control circuit, a second node control circuit, and an output reset circuit, wherein,
• the first node control circuit is respectively connected to the first node, the input terminal, a reset terminal, a first scan voltage terminal, a second scan voltage terminal, a second node, and a second voltage terminal, and is configured to control the connection between the first node and the first scan voltage terminal under the control of the input signal, and control the connection between the first node and the second scan voltage terminal under the control of a reset signal inputted by the reset terminal, and control the connection between the first node and the second voltage terminal under the control of a voltage of the second node;
• the second node control circuit is respectively connected to the first node, the second node, a second clock signal terminal, a gate driving signal output terminal, and a second voltage terminal, and is configured to control a potential of the second node under the control a the second clock signal inputted by the second clock signal terminal, the voltage of the first node, and the gate driving signal outputted by the gate driving signal output terminal;
• and
• the output reset circuit is respectively connected to the second node, the gate driving signal output terminal and the second voltage terminal, and is configured to control the connection between the gate driving signal output terminal and the second voltage terminal under the control of the voltage of the second node.