US 11,777,770 B1Granted

Dynamic shift in outputs of serial and parallel scramblers and descramblers

AssigneeMicrosoft Technology Licensing, LLC

InventorAsaf Levy

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Abstract

Methods, systems are provided for reconfiguring the position of a first tap in a descrambler circuit LFSR after the LFSR has been trained and synchronized with a corresponding scrambler circuit LFSR. A data path from the second tap position to the descrambler output by-passes logic elements located in the data path from the first tap to the descrambler output, thereby reducing delay in the descrambler circuit after the reconfiguration (i.e., the “lock-shift” operation). The tap position change may be communicated by a mode manager to a corresponding scrambler circuit, for applying a matching reconfiguration in the scrambler circuit, either directly via an I/O line or indirectly. The indirect route includes in-band transmissions between two ICs with two sets of self-synchronizing scrambler/descrambler pairs, and is based on monitored receiver LFSR output signals that indicate when a scrambler/descrambler pair is synchronized or whether the output of a descrambler circuit comprises descrambled data.

Claims20

Dependent claims

A system, comprising:

a first descrambler circuit comprising:
a first mode manager;
and
a first receiver having a data input port, the first receiver communicatively coupled to a first transmitter of a first scrambler circuit, the first receiver configured to:
receive a first bit sequence from the first scrambler circuit, the first bit sequence tapped at a first port of a first transmitter linear feedback shift register (LFSR) comprising a first plurality of memory elements in the first scrambler circuit through which the first bit sequence is shifted;
the first descrambler circuit further comprising:
a first receiver LFSR comprising a second plurality of memory elements, the first receiver LFSR configured to:
shift the received first bit sequence through the second plurality of memory elements;
tap a first port of the first receiver LFSR;
and
generate at a first output node of the first receiver LFSR a first output signal configured as a sequential bitwise combination of the received first bit sequence and a bit sequence comprising a sequential bitwise combination of bit sequences tapped from the first port of the first receiver LFSR;
the first mode manager configured to:
detect synchronization between the first transmitter LFSR and the first receiver LFSR based on the first output signal;
and
cause the tap to change from the first port of the first receiver LFSR to a second port of the first receiver LFSR such that the second port is displaced relative to the first port;
the first receiver LFSR further configured to:
generate at a second output node of the first receiver LFSR a second output signal configured as a sequential bitwise combination of a received second bit sequence and a bit sequence tapped from the second port of the first receiver LFSR, wherein a signal propagation time from the second port of the first receiver LFSR to the second output node of the first receiver LFSR is less than the signal propagation time from the first port of the first receiver LFSR to the first output node of the first receiver LFSR.

14 more elements

A method, comprising:

receiving a first bit sequence from a first scrambler circuit, the first bit sequence tapped at a first port of a first transmitter linear feedback shift register (LFSR) comprising a first plurality of memory elements in the first scrambler circuit through which the first bit sequence is shifted;
shifting the received first bit sequence through a second plurality of memory elements in a first receiver LFSR of a first descrambler circuit;
tapping a first port of the first receiver LFSR;
generating at a first output node of the first receiver LFSR a first output signal configured as a sequential bitwise combination of the received first bit sequence and a bit sequence tapped from the first port of the first receiver LFSR;
detecting, by a first mode manager, synchronization between the first transmitter LFSR and the first receiver LFSR based on the first output signal;
causing, by the first mode manager, the tap to change from the first port of the first receiver LFSR to a second port of the first receiver LFSR such that the second port is displaced relative to the first port;
and
generating at a second output node of the first receiver LFSR a second output signal configured as a sequential bitwise combination of a received second bit sequence and a bit sequence comprising a sequential bitwise combination of bit sequences tapped from the second port of the first receiver LFSR;
wherein a signal propagation time from the second port of the first receiver LFSR to the second output node of the first receiver LFSR is less than the signal propagation time from the first port of the first receiver LFSR to the first output node of the first receiver LFSR.

6 more elements

A method comprising:

detecting, by a first mode manager, synchronization of a first receiver LFSR linear feedback shift register (LFSR) and a first transmitter LFSR during a training mode, wherein a first sequence of training bits is tapped at a first port of the first receiver LFSR through which the first sequence of training bits is shifted;
transmitting, by the first mode manager, a lock-shift signal to the first receiver LFSR based on the detected synchronization, wherein the first receiver LFSR is reconfigured to tap a second port of the first receiver LFSR in response to receiving the lock-shift signal;
transmitting, by the first mode manager, a start-training signal to a second transmitter LFSR, wherein the second transmitter LFSR is configured to transmit a second sequence of training bits to a second receiver LFSR in response to receiving the start-training signal;
detecting, by a second mode manager, synchronization of the second receiver LFSR and the second transmitter LFSR during a training mode, wherein the second sequence of training bits is tapped at a first port of the second receiver LFSR through which the second sequence of training bits is shifted;
transmitting, by the second mode manager, a lock-shift signal to the second receiver LFSR, wherein the second receiver LFSR is reconfigured to tap a second port of the second receiver LFSR in response to receiving the lock-shift signal;
transmitting, by the second mode manager, a lock-shift signal to the first transmitter LFSR, wherein the first transmitter LFSR is reconfigured to tap a second port of the first transmitter LFSR in response to receiving the lock-shift signal;
transmitting, by the second mode manager, a switch data-source signal to the first transmitter LFSR, wherein the first transmitter LFSR transmits a first sequence of scrambled data bits to the first receiver LFSR in response to receiving the switch data-source signal;
detecting, by the first mode manager, a first sequence of descrambled data bits output from the first receiver LFSR, wherein the first sequence of descrambled data bits is generated based on descrambling with data bits tapped at the second port of the second receiver LFSR;
transmitting, by the first mode manager, a lock-shift signal to the second transmitter LFSR, wherein the second transmitter LFSR is reconfigured to tap a second port of the second transmitter LFSR in response to receiving the lock-shift signal;
transmitting, by the first mode manager, a switch data-source signal to the second transmitter LFSR, wherein the second transmitter LFSR transmits a second sequence of scrambled data bits to the second receiver LFSR in response to receiving the switch data-source signal;
and
wherein the second receiver LFSR descrambles the second sequence of scrambled data bits and outputs a second sequence of descrambled data bits, and the second sequence of scrambled data bits is descrambled based on a sequence of bits tapped at the second port of the second receiver LFSR.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/727,324Filed 22 Apr 2022
Published: US 2023/0344684 A126 Oct 2023
Granted: 3 Oct 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H04L 25/03866
Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties: using scrambling
H04L 25/03872
Using scrambling: parallel scrambling or descrambling
H04L 25/4902
Using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using…:…
H04L 25/4904
Using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using…:…