US 11,777,701 B2Granted

Phase synchronization circuit, transmission and reception circuit, and integrated circuit

AssigneeSocionext Inc.

InventorMasatoshi Tsuge

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Abstract

A phase synchronization circuit which includes a first delay circuit for adjusting a first delay amount, delaying a first reference clock signal by the first delay amount, and outputting a first delayed reference clock signal. The phase synchronization circuit further includes a first clock control circuit that compares phases of the first delayed reference clock signal and a first output clock signal and generates a first clock control signal based on a result of the comparison; a first clock signal generation circuit that generates the first output clock signal based on the first clock control signal; and a first monitoring circuit that monitors jitter in the first output clock signal and adjusts the first delay amount based on a result of monitoring the jitter in the first output clock signal.

Claims15

Dependent claims

A phase synchronization circuit, comprising:

a first delay circuit for adjusting a first delay amount, the first delay circuit being configured to delay a first reference clock signal by the first delay amount, and output a first delayed reference clock signal;
a first clock control circuit that is configured to compare phases of the first delayed reference clock signal and a first output clock signal and output a first clock control signal based on a result of the comparison;
a first clock signal generation circuit that is configured to receive the first clock control signal and generate the first output clock signal based on the received first clock control signal;
and
a first monitoring circuit that is configured to monitor jitter in the first output clock signal and adjust the first delay amount based on a result of monitoring the jitter in the first output clock signal,
wherein the first clock signal generation circuit includes a voltage controlled oscillator circuit configured to receive the first clock control signal as an input signal, and
wherein the first monitoring circuit is configured to detect a variation amount of the input signal of the voltage controlled oscillator circuit and adjust the first delay amount based on the detected variation amount.

4 more elements

A transmission and reception circuit, comprising:

a first phase synchronization circuit that is configured to generate a first output clock signal;
a first transmission circuit that is configured to perform data transmission based on the first output clock signal;
and
a first reception circuit that is configured to perform data reception based on the first output clock signal, wherein
the first phase synchronization circuit comprises:
a first delay circuit for adjusting a first delay amount, the first delay circuit being configured to delay a first reference clock signal by the first delay amount, and outputs a first delayed reference clock signal;
a first clock control circuit that is configured to compare phases of the first delayed reference clock signal and the first output clock signal and output a first clock control signal based on a result of the comparison;
a first clock signal generation circuit that is configured to receive the first clock control signal and generate the first output clock signal based on the received first clock control signal;
and
a first monitoring circuit that is configured to monitor jitter in the first output clock signal and adjust the first delay amount based on a result of monitoring the jitter in the first output clock signal,
wherein the first clock signal generation circuit includes a voltage controlled oscillator circuit configured to receive the first clock control signal as an input signal, and
wherein the first monitoring circuit is configured to detect a variation amount of the input signal of the voltage controlled oscillator circuit and adjust the first delay amount based on the detected variation amount.

9 more elements

An integrated circuit, comprising:

a first phase synchronization circuit that is configured to generate a first output clock signal;
a first transmission circuit that is configured to transmit first transmission data based on the first output clock signal;
first output clock signal;
a first reception circuit that is configured to receive first reception data based on the first output clock signal;
and
an internal circuit that is configured to output the first transmission data to the first transmission circuit and receive the first reception data from the first reception circuit, wherein
the first phase synchronization circuit comprises:
a first delay circuit for adjusting a first delay amount, the first delay circuit being configured to delay a first reference clock signal by the first delay amount, and output a first delayed reference clock signal;
a first clock control circuit that is configured to compare phases of the first delayed reference clock signal and the first output clock signal and output a first clock control signal based on a result of the comparison;
a first clock signal generation circuit that is configured to receive the first clock control signal and generate the first output clock signal based on the received first clock control signal;
and
a first monitoring circuit that is configured to monitor jitter in the first output clock signal and adjust the first delay amount based on a result of monitoring the jitter in the first output clock signal,
wherein the first clock signal generation circuit includes a voltage controlled oscillator circuit configured to receive the first clock control signal as an input signal, and
wherein the first monitoring circuit is configured to detect a variation amount of the input signal of the voltage controlled oscillator circuit and adjust the first delay amount based on the detected variation amount.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/142,590Filed 6 Jan 2021 · continuation
Priority: 10 Jul 2018
Published: US 2021/0126766 A129 Apr 2021
Granted: 3 Oct 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H04L 7/0037
Correction by delay: delay of clock signal
H03L 7/00
Automatic control of frequency or phase
H03L 7/07
Using a reference signal applied to a frequency- or phase-locked loop: using several loops, e.g. for redundant clock signal generation
H04B 1/403
Circuits: using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency