A processor implemented method for permutation based coding and generating permuted bits and parity equations thereof, the method comprising:
- receiving, via one or more hardware processors and one or more interfaces, an input block of size ‘n’ bits and a data block of size ‘m’ bits, wherein ‘n’ and ‘m’ are positive integers, wherein the data block is permutated at a block level or subblock level using the particulars of the input block at a block level or subblock level respectively;
- calculating, via the one or more hardware processors, a number of bits required to represent the size of data block for one of (i) block level or (ii) subblock level implementation, wherein the size for block level implementation is ‘m’ and size for subblock level implementation is ‘m/l’ bits, wherein ‘l’ is a positive integer such that ‘m/l’ is an integer;
- forming, via the one or more hardware processors and a memory, ‘m’ number of bit groups, to bring about permutation sequences for all the positions in the data block, of a predetermined bit size using the input block for the at least one implementation type, wherein the bit size ‘b’ of each bit group for block level implementation is determined such that (m/(2{circumflex over ( )}b))≤1 and for subblock level implementation it is determined such that ((m/l)/(2{circumflex over ( )}b))≤1;
- converting, via the one or more hardware processors and the memory, the ‘m’ bit groups into equivalent decimal values using any standard number system conversion method like doubling method or positional notation method;
- determining, via the one or more hardware processors and the memory, one or more collision resolution rules with multiple step sizes for the at least one implementation type to resolve collisions occurring during a final permutation sequence derivation;
- deriving, via the one or more hardware processors and the memory, a final permutation sequence for one of (i) each data subblock or (ii) the data block using the converted decimal values, the determined one or more collision resolution rules and modulo arithmetic, wherein the derived final permutation sequence comprises all corresponding data bit positions distinctly, wherein the converted decimal values, in conjunction with modulo arithmetic, are used sequentially to denote distinct positions in the final permutation sequence and collisions occurred, while using a converted decimal value to represent a distinct position in the final permutation sequence, are handled by adding the next available step size value, of the multiple steps, to the subsequent colliding value and step size 1 is repeated at the end, if all the multiple step sizes are used and collision still persist, until a value representing a distinct position in the final permutation sequence is attained;
- and
- using the final permutation sequence, performing, via the one or more hardware processors and the memory, one of:
- performing, via the one or more hardware processors and memory, permutation of one of (i) each data subblock or (ii) the data block to obtain permuted bits using the final permutation sequence;
- or
- generating, via the one or more hardware processors and the memory, parity equations for one of (i) each data subblock or (ii) the data block using the final permutation sequence.