Analog-to-digital converter capable of cancelling sampling noise

An analog-to-digital converter capable of cancelling sampling noise, comprising:

• a sampling circuit, a sampling noise cancelling circuit, a comparator and a logic circuit, wherein
• the sampling circuit is configured to acquire an analog input signal;
• the sampling noise cancelling circuit has an input end connected with an output end of the sampling circuit, and is configured to cancel noise generated by the sampling circuit;
• the comparator has an input end connected with an output end of the sampling noise cancelling circuit, and an output end connected with an input end of the logic circuit, and the comparator is configured to compare magnitudes of output signals of the sampling noise cancelling circuit and output a comparison result to the logic circuit;
• the logic circuit has an output end connected with the sampling circuit, and is configured to output a digital output signal, and configured to process the comparison result to obtain a control signal by which an output voltage of the sampling circuit is controlled;
• the sampling circuit includes a first sampling capacitor array, a first switch and a second switch;
• the sampling noise cancelling circuit includes an amplifier, a second capacitor and a third switch;
• the first sampling capacitor array has a lower plate connected respectively with one end of the second switch and one of a reference voltage or the logic circuit, and an upper plate connected separately with one end of the first switch and an input end of the amplifier, the other end of the first switch is grounded or connected with a DC voltage, and the other end of the second switch is connected with the analog input signal;
• the input end of the amplifier is connected with the one end of the first switch, and an output end of the amplifier is connected with a lower plate of the second capacitor;
• an upper plate of the second capacitor is connected separately with one end of the third switch and the input end of the comparator, and the other end of the third switch is grounded or connected with a DC voltage;
• the first switch and the third switch are grounded;
• and in a time period of t0-t1, the first switch, the second switch and the third switch are on, the analog input signal is followed and stored on the first sampling capacitor array, the input end of the amplifier and the upper plate of the second capacitor are grounded, and a voltage across the second capacitor is cleared;
• at the time t1, the first switch is off, and the input signal at the time t1 Vin(t1) and the sampling noise vns1 are stored together on the first sampling capacitor array;
• and the upper plate of the first sampling capacitor array is open, and a voltage across the first sampling capacitor array is kept constantly at Vin(t1)+vns1;
• in a time period of t1-t2, the first switch is in an off state, the third switch is in an on state, the input signal Vin in the time period of t1-t2 is still connected with the lower plate of the first sampling capacitor array, the voltage across the first sampling capacitor is kept unchanged, and a voltage on the input end of the amplifier is a difference between Vin and the voltage across the first sampling capacitor array, i.e., Vin-Vin(t1)−vns1, and is amplified by A times and then stored on the capacitor C2, wherein A is a gain of the amplifier;
• at the time t2, the third switch is off, a noise Vns2 of the third switch is fixed on the second capacitor, the input signal at the time t2 is Vin(t2), and a total voltage acquired by the second capacitor is A·[Vin(t2)−Vin(t1)−vns1]+vns2;
• after the time t2, a conversion process of the analog-to-digital converter begins, the comparator performs comparisons for multiple times, and the logic circuit feeds a result of each comparison back to the lower plate of the first sampling capacitor array, so that a voltage on the input end of the comparator is pulled down towards 0;
• and at a time when the conversion is ended, an equivalent signal at the lower plate of the first sampling capacitor array is the digital output signal Dout;
• and since the voltage on the input end of the comparator is 0 at the end of conversion, the digital ouput signal Dout can be obtained as
• Dout=Vin(t2)+vns2/A.