Fractional divider with phase shifter and fractional phase locked loop including the same

A fractional phase locked loop comprising:

• processing circuitry configured to execute machine-readable instructions that, when executed by a processor, cause the process:
• generate a phase detection signal based on a reference clock signal and a feedback clock signal,
• to generate an output control signal based on the phase detection signal,
• to generate a plurality of clock signals based on the output control signal, and to output one of the plurality of clock signals as an output clock signal, phases of the plurality of clock signals partially overlapping each other, and
• to generate the feedback clock signal by dividing the output clock signal,
• wherein the processing circuitry is configured
• to generate a first division clock signal based on the output clock signal and a first control signal,
• to generate a delta-sigma modulation signal based on the first division clock signal and a frequency control word,
• to generate a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal, the second control signal corresponding to a quantization noise of the generation of the delta-sigma modulation signal,
• to generate the second control signal and a digital control word based on the phase detection signal and the quantization noise of the generation of the delta-sigma modulation signal, and
• to generate the feedback clock signal based on the second division clock signal and the digital control word.

A fractional divider comprising:

• processing circuitry configured to execute machine-readable instructions that, when executed by the processing circuitry, cause the processing circuitry,
• to receive one of a plurality of clock signals as an input clock signal, and to generate a first division clock signal based on the input clock signal and a first control signal, phases of the plurality of clock signals partially overlapping each other, the first division clock signal being obtained by an integer-division of the input clock signal,
• to generate a delta-sigma modulation signal based on the first division clock signal and a frequency control word, the frequency control word including an integer part and a fractional part;
• to generate the first control signal by adding the integer part of the frequency control word and the delta-sigma modulation signal;
• to generate a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal, the second control signal corresponding to a first portion of a quantization error signal corresponding to a quantization noise of the generation of the delta-sigma modulation signal, the second division clock signal being obtained by a fractional-division of the input clock signal;
• to generate a difference signal by subtracting the delta-sigma modulation signal from the fractional part of the frequency control word;
• to generate the quantization error signal by integrating the difference signal, and to generate the second control signal and a digital control word based on a third control signal, the third control signal corresponding to a second portion of the quantization error signal different from the first portion of the quantization error signal;
• and
• to generate a final division clock signal based on the second division clock signal and the digital control word, the final division clock signal being obtained by a fractional-division of the input clock signal,
• wherein:
• the processing circuitry is configured to generate the final division clock signal by adding a time delay to the first division clock signal,
• the time delay corresponds to the quantization noise of the generation of the delta-sigma modulation signal, and includes a coarse time delay and a fine time delay, and
• in response to the time delay being represented as a digital value including (M+K) bits, where each of M and K is a natural number, the processing circuitry is configured to generate the coarse time delay corresponding to upper M bits among the (M+K) bits, and the processing circuitry is configured to generate the fine time delay corresponding to lower K bits among the (M+K) bits.