Clock generation circuit and semiconductor apparatus using the clock generation circuit
AssigneeSK hynix Inc.
InventorsSung Hyun Song, Young Suk Seo
Life of this patent
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Abstract
A delay circuit including a first output clock generation circuit and a second output clock generation circuit. The first output clock generation circuit generates a first output clock signal by mixing phases of a first clock signal and a second clock signal based on an (n+1)-th generated delay control signal. The second output clock generation circuit generates a second output clock signal by mixing the phases of the first and second clock signals based on both an n-th generated delay control signal and the (n+1)-th generated delay control signal.
Claims15
A semiconductor device comprising a delay loop circuit, the delay loop circuit comprising:
- a coarse delay circuit configured to generate a first delay clock signal and a second delay clock signal by delaying a reference clock signal based on a coarse delay control signal;
- a fine delay circuit configured to generate a feedback delay locked clock signal and an output delay locked clock signal by mixing phases of the first delay clock signal and the second delay clock signal based on a fine delay control signal, the feedback delay locked clock signal being generated based on an (n+1)-th generated fine delay control signal and n being a positive integer;
- a replica configured to generate a feedback clock signal by delaying the feedback delay locked clock signal by a modeled delay time;
- a phase detector configured to generate a phase detection signal by comparing phases of the reference clock signal and the feedback clock signal;
- and
- a delay control circuit configured to generate the coarse delay control signal and the fine delay control signal based on the phase detection signal.
A semiconductor device comprising a delay loop circuit, the delay loop circuit comprising:
- a coarse delay circuit configured to generate a first delay clock signal and a second delay clock signal by delaying a reference clock signal based on a coarse delay control signal;
- a fine delay circuit configured to generate a feedback delay locked clock signal and an output delay locked clock signal by mixing phases of the first delay clock signal and the second delay clock signal based on a fine delay control signal, the output delay locked clock signal being changed independently of the feedback delay locked clock signal;
- a replica configured to generate a feedback clock signal by delaying the feedback delay locked clock signal by a modeled delay time;
- a phase detector configured to generate a phase detection signal by comparing phases of the reference clock signal and the feedback clock signal;
- and
- a delay control circuit configured to generate the coarse delay control signal and the fine delay control signal based on the phase detection signal.
Dependencies are inferred from the claim text.