US 11,777,502 B2Granted

Logic circuit and semiconductor device formed using unipolar transistor

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsHiroki Inoue, Munehiro Kozuma, Takeshi Aoki, Shuji Fukai, Fumika Akasawa, Sho Nagao

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Abstract

A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.

Claims16

Dependent claims

A semiconductor device comprising:

first to eighth transistors;
first and second capacitors;
first and second wirings;
first and second input terminals;
and
first and second output terminals,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one terminal of the first capacitor, and the first output terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein a gate of the first transistor is electrically connected to a gate of the fourth transistor, one of a source and a drain of the eighth transistor, one of a source and a drain of the seventh transistor, one terminal of the second capacitor, and a gate of the sixth transistor,
wherein a gate of the second transistor is electrically connected to the other terminal of the first capacitor, one of a source and a drain of the fourth transistor, one of a source and a drain of the third transistor, a gate of the eighth transistor, and a gate of the fifth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring,
wherein a gate of the third transistor is electrically connected to the second input terminal,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the second wiring,
wherein a gate of the seventh transistor is electrically connected to the first input terminal,
wherein one of a source and a drain of the fifth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor, the other terminal of the second capacitor, and the second output terminal, and
wherein the other of the source and the drain of the sixth transistor is electrically connected to the second wiring.

17 more elements

A semiconductor device comprising:

first to sixth transistors;
first and second capacitors;
first and second wirings;
first and second input terminals;
and
first and second output terminals,
wherein one of a source and the drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, a gate of the fourth transistor, one terminal of the first capacitor, and the first output terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the fourth transistor, one of a source and a drain of the fifth transistor, one terminal of the second capacitor, and the second output terminal,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the third transistor and the other terminal of the first capacitor,
wherein a gate of the third transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the second input terminal,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the second wiring,
wherein a gate of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor and the other terminal of the second capacitor,
wherein a gate of the sixth transistor is electrically connected to the second wiring, and
wherein the other of the source and the drain of the sixth transistor is electrically connected to the first input terminal.

15 more elements

A semiconductor device comprising:

first to tenth transistors;
first and second capacitors;
first and second wirings;
first to fourth input terminals;
and
first and second output terminals,
wherein one of a source and the drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one terminal of the first capacitor, and the first output terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein a gate of the first transistor is electrically connected to a gate of the fifth transistor, one of a source and a drain of the tenth transistor, one of a source and a drain of the ninth transistor, one terminal of the second capacitor, and a gate of the seventh transistor,
wherein a gate of the second transistor is electrically connected to the other terminal of the first capacitor, one of a source and a drain of the fourth transistor, one of a source and a drain of the third transistor, one of a source and a drain of the fifth transistor, a gate of the tenth transistor, and a gate of the sixth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring,
wherein a gate of the fourth transistor is electrically connected to the fourth input terminal,
wherein a gate of the third transistor is electrically connected to the second input terminal,
wherein the other of the source and the drain of the tenth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the ninth transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the second wiring,
wherein a gate of the ninth transistor is electrically connected to the third input terminal,
wherein a gate of the eighth transistor is electrically connected to the first input terminal,
wherein one of a source and a drain of the sixth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor, the other terminal of the second capacitor, and the second output terminal, and
wherein the other of the source and the drain of the seventh transistor is electrically connected to the second wiring.

21 more elements

A semiconductor device comprising:

first to tenth transistors;
first and second capacitors;
first and second wirings;
first to fourth input terminals;
and
first and second output terminals,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one terminal of the first capacitor, and the first output terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein a gate of the first transistor is electrically connected to a gate of the fifth transistor, one of a source and a drain of the tenth transistor, one of the source and a drain of the eighth transistor, one of a source and a drain of the ninth transistor, one terminal of the second capacitor, and a gate of the seventh transistor,
wherein a gate of the second transistor is electrically connected to the other terminal of the first capacitor, one of a source and a drain of the fourth transistor, one of a source and a drain of the fifth transistor, a gate of the tenth transistor, and a gate of the sixth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring,
wherein a gate of the fourth transistor is electrically connected to the fourth input terminal,
wherein a gate of the third transistor is electrically connected to the second input terminal,
wherein the other of the source and the drain of the tenth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the second wiring,
wherein a gate of the eighth transistor is electrically connected to the first input terminal,
wherein a gate of the ninth transistor is electrically connected to the third input terminal,
wherein one of a source and a drain of the sixth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor, the other terminal of the second capacitor, and the second output terminal, and
wherein the other of the source and the drain of the seventh transistor is electrically connected to the second wiring.

21 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/441,804Filed 12 Mar 2020
Priority: JP 2019-06678529 Mar 2019
Published: US 2022/0173737 A12 Jun 2022
Granted: 3 Oct 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H03K 19/08
Using specified components: using semiconductor devices
H03K 17/063
Modifications for ensuring a fully conducting state: in field-effect transistor switches
H03K 17/56
Characterised by the components used: by the use, as active elements, of semiconductor devices
H03K 19/0185
Coupling arrangements; Interface arrangements: using field effect transistors only