Voltage sensing and biasing for wide supply range integrated circuit transceivers

A circuit arrangement comprising:

• a biasing circuit configured to generate a pbias voltage and an nbias voltage in response to a supply voltage level, wherein:
• the pbias voltage is greater than a difference between the supply voltage level and a reliability limit and less than one-half the supply voltage level, and the nbias voltage is greater than one-half the supply voltage level and less than the reliability limit in response to the supply voltage level being greater than the reliability limit, and
• the pbias voltage is greater than ground level and less than twice a gate-source threshold of a first p-type transistor providing the pbias voltage, and the nbias voltage is greater than twice a gate-source threshold of a first n-type transistor providing the nbias voltage and less than the supply voltage level in response to the supply voltage level being less than the reliability limit;
• and
• a transmitter that is controllable to operate in a first voltage mode that is greater than the reliability limit or a second voltage mode that is less than the reliability limit, wherein a driver of the transmitter is coupled to receive the pbias voltage and the nbias voltage.

A circuit arrangement, comprising:

• a first biasing circuit configured to generate a final pbias voltage, a final nbias voltage, and a sense signal in response to a supply voltage level, wherein:
• the final nbias voltage is greater than one-half the supply voltage level and less than a reliability limit, and the final pbias voltage is greater than a difference between the supply voltage level and the reliability limit and less than one-half the supply voltage level, in response to the supply voltage level being greater than the reliability limit,
• the final pbias voltage is pulled to ground level, and the final nbias voltage is pulled to the supply voltage level, in response to the supply voltage level being less than the reliability limit, and
• a voltage level of the sense signal is less than the supply voltage level;
• a receiver that is controllable to operate in a first voltage mode that is greater than the reliability limit or operate in a second voltage mode that is less than the reliability limit, wherein the receiver is coupled to receive the final pbias voltage and the final nbias voltage;
• a power-on-reset circuit coupled to receive the sense signal from the biasing circuit and configured to force output from the receiver to a constant logic value during ramp-up of the supply voltage;
• a second biasing circuit configured to generate a transmit-pbias voltage and a transmit-nbias voltage in response to the supply voltage level, wherein:
• the transmit-pbias voltage is greater than a difference between the supply voltage level and the reliability limit and less than one-half the supply voltage level, and the transmit-nbias voltage is greater than one-half the supply voltage level and less than the reliability limit in response to the supply voltage level being greater than the reliability limit, and
• the transmit-pbias voltage is greater than ground level and less than twice a gate-source threshold of a first p-type transistor providing the transmit-pbias voltage, and the transmit-nbias voltage is greater than twice a gate-source threshold of a first n-type transistor providing the transmit-nbias voltage and less than the supply voltage level in response to the supply voltage level being less than the reliability limit;
• and
• a transmitter that is controllable to operate in the first voltage mode or the second voltage mode, wherein a driver of the transmitter is coupled to receive the transmit-pbias voltage and the transmit-nbias voltage.