Comparator and decision feedback equalization circuit

A comparator, comprising a first-stage circuit, a second-stage circuit, a first switching circuit and a second switching circuit, wherein the first-stage circuit comprises a first input circuit and a second input circuit;

• the first input circuit is connected with the first switching circuit, the second input circuit is connected with the second switching circuit;
• the first switching circuit and the second switching circuit are further connected with a ground terminal or a power terminal respectively, the first input circuit and the second input circuit are further connected with the ground terminal or the power terminal respectively, the first input circuit and the second input circuit are both further connected with the second-stage circuit;
• the second-stage circuit is connected with the power terminal or the ground terminal;
• the first switching circuit is configured to control conduction of the first input circuit according to a first feedback signal, a second feedback signal and a clock signal;
• the second switching circuit is configured to control conduction of the second input circuit according to the first feedback signal, the second feedback signal and the clock signal;
• the first input circuit is configured to generate a first differential signal according to an input signal and a first reference signal in a sampling phase when being switched on;
• the second input circuit is configured to generate a second differential signal according to the input signal and a second reference signal in a sampling phase when being switched on;
• and
• the second-stage circuit is configured to amplify and latch the first differential signal or the second differential signal in a regeneration phase to output a comparison signal;
• wherein the first input circuit comprises a first input transistor, a second input transistor and a third input transistor;
• a first terminal of the first input transistor and a first terminal of the second input transistor are respectively connected with the second-stage circuit;
• a control terminal of the third input transistor serves as the control terminal of the first input circuit, a second terminal of the third input transistor is connected with the ground terminal or the power terminal;
• a second terminal of the first input transistor and a second terminal of the second input transistor are both connected with a first terminal of the third input transistor;
• the first to third input transistors are NMOS transistors or PMOS transistors;
• a control terminal of the first input transistor receives the input signal, a control terminal of the second input transistor receives the first reference signal;
• and
• when the third input transistor is triggered by the clock signal to be in a switched-on state, the first input transistor and the second input transistor generate the first differential signal according to the input signal and the first reference signal, and output the first differential signal to the second-stage circuit.

A comparator, comprising a first-stage circuit, a second-stage circuit, a first switching circuit and a second switching circuit, wherein the first-stage circuit comprises a first input circuit and a second input circuit;

• the first input circuit is connected with the first switching circuit, the second input circuit is connected with the second switching circuit;
• the first switching circuit and the second switching circuit are further connected with a ground terminal or a power terminal respectively, the first input circuit and the second input circuit are further connected with the ground terminal or the power terminal respectively, the first input circuit and the second input circuit are both further connected with the second-stage circuit;
• the second-stage circuit is connected with the power terminal or the ground terminal;
• the first switching circuit is configured to control conduction of the first input circuit according to a first feedback signal, a second feedback signal and a clock signal;
• the second switching circuit is configured to control conduction of the second input circuit according to the first feedback signal, the second feedback signal and the clock signal;
• the first input circuit is configured to generate a first differential signal according to an input signal and a first reference signal in a sampling phase when being switched on;
• the second input circuit is configured to generate a second differential signal according to the input signal and a second reference signal in a sampling phase when being switched on;
• and
• the second-stage circuit is configured to amplify and latch the first differential signal or the second differential signal in a regeneration phase to output a comparison signal;
• wherein the second input circuit comprises a fourth input transistor, a fifth input transistor and a sixth input transistor;
• a first terminal of the fourth input transistor and a first terminal of the fifth input transistor are connected with the second-stage circuit respectively;
• a control terminal of the sixth input transistor serves as the control terminal of the second input circuit, a second terminal of the sixth input transistor is connected with the ground terminal or the power terminal;
• a second terminal of the fourth input transistor and a second terminal of the fifth input transistor are both connected with a first terminal of the sixth input transistor;
• the fourth to sixth input transistors are NMOS transistors or PMOS transistors;
• a control terminal of the fourth input transistor receives the input signal, a control terminal of the fifth input transistor receives the second reference signal;
• and
• when the sixth input transistor is triggered by the clock signal to be in a switched-on state, the fourth input transistor and the fifth input transistor generate the second differential signal according to the input signal and the second reference signal, and output the second differential signal to the second-stage circuit.