US 11,777,481 B2Granted

Noise-tolerant delay circuit

AssigneeSilanna Asia Pte Ltd

InventorsJoseph H. Colles, Steven E. Rosenbaum, Stuart B. Molin

Life of this patent

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Abstract

In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.

Claims20

Dependent claims

A delay circuit comprising:

a delay element that comprises:
an input configured to receive an input signal;
an output configured to produce an output signal that is delayed from the input signal;
a first set of transistors that includes a first current source transistor, a first cascode transistor, and a first control transistor;
a second set of transistors that includes a second control transistor, a second cascode transistor, and a second current source transistor;
and
a capacitor that has a node that is electrically connected between the first control transistor and the second control transistor;
and wherein:
the first set of transistors form a first current source electrically connected to the capacitor and configured to generate a first current to generate a ramp signal with a first slope under control of the first control transistor;
the second set of transistors form a second current source electrically connected to the capacitor and configured to generate a second current to generate the ramp signal with a second slope under control of the second control transistor;
and
the delay circuit transitions a state of the output signal based on a voltage level of the ramp signal.

9 more elements

A delay circuit comprising:

a delay element that comprises:
an input configured to receive an input signal;
an output configured to produce an output signal that is delayed from the input signal;
a capacitor;
a first set of transistors that forms a first current source configured to generate a first current to generate a ramp signal with a first slope under control of the first set of transistors;
a second set of transistors that forms a second current source configured to generate a second current to generate the ramp signal with a second slope under control of the second set of transistors, and wherein the capacitor has a node that is electrically connected between the first set of transistors and the second set of transistors;
a first bias transistor configured to cause the ramp signal to be biased to a first voltage when the first set of transistors is activated at a start of a first time period, which causes the ramp signal to ramp during the first time period from the first voltage towards a second voltage, and which causes the ramp signal to be substantially linear during an initial portion of the first time period;
and
a second bias transistor configured to cause the ramp signal to be biased to the second voltage when the second set of transistors is activated at a start of a second time period, which causes the ramp signal to ramp during the second time period from the second voltage towards the first voltage, and which causes the ramp signal to be substantially linear during an initial portion of the second time period;
and wherein:
the delay circuit transitions a state of the output signal based on a voltage level of the ramp signal.

8 more elements

A delay circuit comprising;

a reference current generator configured to generate first bias control signals and second bias control signals, the first bias control signals and the second bias control signals being based on a reference current that is generated in the reference current generator and that is dependent on a first voltage and a resistance of a resistor;
and
a delay stage having a first delay element and a second delay element electrically connected in series;
and wherein:
the first delay element and the second delay element each comprise:
a capacitor having a capacitance;
a first set of transistors configured to form a first current source when activated, the first current source generating a first current about equal to the reference current and being electrically connected to the capacitor to generate a ramp signal with a first slope during a first time period;
a second set of transistors configured to form a second current source when activated, the second current source generating a second current about equal to the reference current and being electrically connected to the capacitor to generate the ramp signal with a second slope during a second time period;
a first bias transistor configured to cause the ramp signal to be biased to a second voltage when the first set of transistors is activated at a start of the first time period, which causes the ramp signal to ramp during the first time period from the second voltage towards the first voltage, and which causes the ramp signal to be substantially linear during an initial portion of the first time period;
a second bias transistor configured to cause the ramp signal to be biased to the first voltage when the second set of transistors is activated at a start of the second time period, which causes the ramp signal to ramp during the second time period from the first voltage towards the second voltage, and which causes the ramp signal to be substantially linear during an initial portion of the second time period;
and
an output set of transistors configured to produce an output signal when the ramp signal ramps to a threshold voltage at an end of the initial portion of the first time period and when the ramp signal ramps to the threshold voltage at an end of the initial portion of the second time period;
the output signal of the first delay element is provided as an input signal for the second delay element;
the output signal of the second delay element is delayed from an input signal of the first delay element by a stage delay time period;
the stage delay time period is determined substantially by the resistance of the resistor and the capacitance of the capacitor;
and
the stage delay time period is substantially independent of the first voltage and a temperature of the delay circuit.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/823,019Filed 29 Aug 2022 · continuation
Priority: 23 Nov 2020
Published: US 2022/0166418 A129 Dec 2022
Granted: 3 Oct 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03K 5/134
Using a chain of active delay devices: with field-effect transistors
H03K 5/13
Manipulating of pulses not covered by one of the other main groups of this subclass: arrangements having a single output and transforming input…
H03K 2005/00202
Using FET's: using current mirrors
H03K
Pulse technique

Family

Application63/198,931Us provisional application · filed 23 Nov 2020
Application17/454,207Parent of this continuation · filed 9 Nov 2021
US 2022/0416775 A1Pre-grant publication · published 29 Dec 2022
US 11,451,220 B2Parent of this continuation
US 2022/0166418 A1Published application
US 11,777,481 B2This patent

From the US filing history. Foreign family members aren’t listed.