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US 11,777,474 B2Granted
Signal generation circuit having minimum delay, semiconductor apparatus using the same, and signal generation method
AssigneeSK hynix Inc.
InventorsYoung Ouk Kim, Gyu Tae Park
Life of this patent
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Abstract
A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
Claims16
A semiconductor apparatus comprising:
- a delay locked loop circuit configured to compare the phase of a reference clock signal to the phase of a feedback clock signal generated by delaying a first output clock signal, and generate a delayed clock signal by variably delaying the reference clock signal;
- a clock divider configured to generate at least a first divided clock signal and a second divided clock signal by dividing the delayed clock signal;
- and
- a duty correction circuit configured to generate the first output clock signal and a second output clock signal by delaying the first and second divided clock signals, compare the phases of the first and second output clock signals to adjust a delay time of the second output clock signal by a first time, and then decrease a delay time of the first output clock signal and the delay time of the second output clock signal by a second time.
1 more element
A semiconductor apparatus comprising:
- a delay locked loop circuit configured to generate a delayed clock signal by delaying a reference clock signal, and compare the phase of the reference clock signal to the phase of a feedback clock signal generated by delaying the delayed clock signal and change the time by which the reference clock signal is delayed;
- a multi-phase clock generation circuit configured to generate at least a first output clock signal and a second output clock signal by dividing the frequency of the delayed clock signal;
- a clock distribution network configured to drive the first and second output clock signals and output a first distribution clock signal and a second distribution clock signal;
- and
- a duty correction circuit configured to generate a first transmission clock signal and a second transmission clock signal by delaying the first and second distribution clock signals, compare the phases of the first and second transmission clock signals to adjust a delay time of the second distribution clock signal by a first time, and then decrease a delay time of the first distribution clock signal and the delay time of the second distribution clock signal by a second time.
2 more elements
Dependencies are inferred from the claim text.