Transistors having vertical nanostructures

A semiconductor device, comprising:

• a first source/drain feature and a second source/drain feature;
• a plurality of channel members extending between the first source/drain feature and the second source/drain feature along a first direction;
• a gate structure disposed over and wrapping around the plurality of channel members;
• and
• a first isolation feature and a second isolation feature directly below the plurality of channel members,
• wherein a portion of the gate structure is disposed between the first isolation feature and the second isolation feature.

A method, comprising:

• depositing a mandrel layer over a substrate;
• forming a fin structure that includes a top portion formed from the mandrel layer, a bottom portion formed from the substrate, and a hard mask feature over the top portion;
• conformally depositing an isolation layer over the fin structure;
• recessing the isolation layer to expose sidewalls of the top portion of the fin structure;
• epitaxially depositing a first semiconductor layer over the exposed sidewalls of the top portion;
• epitaxially depositing a second semiconductor layer over the first semiconductor layer;
• forming a dummy gate stack over a channel region of the fin structure;
• recessing a source/drain region of the fin structure to form a source/drain recess;
• forming a source/drain feature in the source/drain recess;
• depositing a dielectric layer over the source/drain feature;
• planarizing the dielectric layer to expose the dummy gate stack;
• selectively removing the dummy gate stack;
• selectively removing the second semiconductor layer and the top portion of the fin structure;
• and
• depositing a gate structure over the first semiconductor layer.