Vertical transistors for ultra-dense logic and memory applications

An apparatus, comprising:

• a first region in an integrated circuit structure, the first region comprising:
• a MOS transistor, comprising a single crystal semiconductor;
• and
• a conductive interconnect coupled with the MOS transistor;
• and
• a second region in the integrated circuit structure, above the first region, the second region comprising:
• a vertical transistor coupled with the conductive interconnect, the vertical transistor comprising:
• a material stack, comprising a source material, a drain material, and a channel material therebetween;
• a gate electrode adjacent to a sidewall of the material stack, the sidewall comprising the channel material and at least a partial thickness of both the source material and the drain material;
• a gate dielectric between the sidewall of the material stack and the gate electrode;
• a first metallization over a first area of the material stack and in contact with the gate electrode;
• and
• a second metallization adjacent to the first metallization, the second metallization over a second area of the material stack and in contact with the source material or the drain material.

An apparatus, comprising:

• a material stack in a vertical transistor structure, comprising a source material, a drain material, and a channel material therebetween;
• a gate electrode adjacent to a sidewall of the material stack, the sidewall comprising the channel material and at least a partial thickness of both the source material and the drain material;
• a gate dielectric between the sidewall of the material stack and the gate electrode;
• a first metallization over a first area of the material stack and in direct contact with the gate electrode;
• and
• a second metallization adjacent to the first metallization, the second metallization over a second area of the material stack and in direct contact with the source material or the drain material.