Semiconductor device

A semiconductor device, comprising:

• a semiconductor member including
• a first semiconductor region of a first conductivity type,
• a second semiconductor region of the first conductivity type, and
• a third semiconductor region provided between the first semiconductor region and the second semiconductor region, the third semiconductor region being of a second conductivity type;
• a first electrode electrically connected to the first semiconductor region;
• a second electrode electrically connected to the second semiconductor region;
• a gate electrode;
• a gate terminal electrically connected to the gate electrode;
• a first conductive member electrically insulated from the first electrode, the second electrode, and the gate electrode, a first distance between the gate electrode and the third semiconductor region being less than a second distance between the first conductive member and the third semiconductor region;
• a first terminal electrically connected to the first conductive member;
• and
• a first insulating member including
• a first insulating region between the third semiconductor region and the gate electrode, and
• a second insulating region between the gate electrode and the first conductive member;
• a second signal being inputtable to the first terminal and being switched at a different timing from a first signal input to the gate terminal;
• and
• a second conductive member,
• wherein
• a direction from the first electrode toward the second electrode is along a first direction,
• the first semiconductor region includes a first partial region a second partial region, and a third partial region,
• a direction from the first partial region toward t second partial region is along a second direction crossing the first direction,
• the second direction is along a face of the first electrode opposite to the first semiconductor region,
• the third partial region is between the first partial region and the second semiconductor region in the first direction,
• the third semiconductor re on is between the third partial region and the second semiconductor region in the first direction,
• a direction from the third semiconductor region toward the gate electrode is along the second direction,
• at least a portion of the gate electrode is between the second partial region and the second electrode in the first direction,
• in the second direction, the gate electrode is between the third partial region and the first conductive member,
• a direction from a portion of the third partial region toward the second conductive member is along the second direction,
• in the first direction, the second conductive member is between the second partial region avid the gate electrode,
• in the first direction, the second conductive member is between the second partial region and the first conductive member,
• the first insulating member includes a third insulating region and a fourth insulating region,
• the third insulating region is between the third partial region and the second conductive member in the second direction,
• the fourth insulating region is between the second partial region and the second conductive member in the first direction,
• the second conductive member is electrically connected to the second electrode or electrically connectable to the second electrode, and
• at least a portion of the gate electrode is located between the third semiconductor region and the first conductive member in the second direction.