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US 11,777,016 B2Granted
Method of forming backside power rails
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPing-Wei Wang, Chih-Chuan Yang, Yu-Kuan Lin, Choh Fei Yeap
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Abstract
A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.
Claims20
A semiconductor structure, comprising:
- a first bottom semiconductor feature and a second bottom semiconductor feature disposed on a backside dielectric layer;
- a first vertical stack of nanostructures disposed over the first bottom semiconductor feature;
- a second vertical stack of nanostructures disposed over the second bottom semiconductor feature;
- a first epitaxial source/drain feature extending between the first vertical stack of nanostructures and the second vertical stack of nanostructures along a direction;
- and
- a backside contact extending through the backside dielectric layer to couple to the first epitaxial source/drain feature,
- wherein a portion of the backside contact extends between the first bottom semiconductor feature and the second bottom semiconductor feature along the direction.
4 more elements
A method, comprising:
- receiving a composite substrate that includes:
- a semiconductor substrate,
- a first silicon germanium (SiGe) layer over the semiconductor substrate,
- a first silicon (Si) layer over the first silicon germanium (SiGe) layer,
- a second SiGe layer over the first Si layer, and
- a second Si layer over the second SiGe layer;
- patterning the second Si layer to form a fin;
- forming a dummy gate stack over a channel region of the fin;
- recessing a source region and a drain region of the fin to form a source opening and a drain opening, the source region and the drain region sandwiching the channel region;
- depositing a mask film over the source opening, the dummy gate stack and the drain region;
- patterning the mask film to expose the source opening;
- after the patterning of the mask film, selectively extending the source opening through the second SiGe layer to form an extended source opening;
- with the patterned mask film in place, forming a semiconductor plug in the extended source opening;
- forming an epitaxial source feature over the semiconductor plug and an epitaxial drain feature in the drain opening;
- planarizing the composite substrate from a surface of the semiconductor substrate until the semiconductor plug is exposed;
- after the planarizing, replacing the second SiGe layer with a backside dielectric layer;
- and
- replacing the semiconductor plug with a backside contact.
15 more elements
A method, comprising:
- receiving a composite substrate that includes:
- a semiconductor substrate,
- a first silicon germanium (SiGe) layer over the semiconductor substrate,
- a silicon (Si) layer over the first silicon germanium (SiGe) layer,
- a second SiGe layer over the Si layer, and
- a semiconductor layer stack over the second SiGe layer, the semiconductor layer stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
- patterning the semiconductor layer stack to form a fin-shaped structure;
- forming a dummy gate stack over a channel region of the fin-shaped structure;
- recessing a source region and a drain region of the fin-shaped structure to form a source opening and a drain opening, the source region and the drain region sandwiching the channel region;
- depositing a mask film over the source opening, the dummy gate stack and the drain region;
- patterning the mask film to expose the source opening;
- after the patterning of the mask film, selectively extending the source opening through the second SiGe layer to form an extended source opening;
- with the patterned mask film in place, forming a semiconductor plug in the extended source opening;
- forming an epitaxial source feature over the semiconductor plug and an epitaxial drain feature in the drain opening;
- planarizing the composite substrate from a surface of the semiconductor substrate until the semiconductor plug is exposed;
- after the planarizing, replacing the second SiGe layer with a backside dielectric layer;
- and
- replacing the semiconductor plug with a backside contact.
15 more elements
Dependencies are inferred from the claim text.